Revert sblk/sblink change, use sblk like the rest of the codebase does.

[coreboot.git] / src / southbridge / amd / rs780 / rs780_gfx.c

diff --git a/src/southbridge/amd/rs780/rs780_gfx.c b/src/southbridge/amd/rs780/rs780_gfx.c
index 88cb935de8faf62ea43a6a81e86f5eef09049fc0..a9801a17cd4283c6fbb95e3dda7c56d18ba190ca 100644 (file)
--- a/src/southbridge/amd/rs780/rs780_gfx.c
+++ b/src/southbridge/amd/rs780/rs780_gfx.c
@@ -35,7 +35,7 @@
 #include <delay.h>
 #include <cpu/x86/msr.h>
 #include "rs780.h"
-
+extern int is_dev3_present(void);
 void set_pcie_reset(void);
 void set_pcie_dereset(void);
 
@@ -304,7 +304,7 @@ static void internal_gfx_pci_dev_init(struct device *dev)
        volatile u32 * pointer;
        int i;
        u16 command;
-       u32 value;
+       u32 value, sblk;
        u16 deviceid, vendorid;
        device_t nb_dev = dev_find_slot(0, 0);
        device_t k8_f2 = dev_find_slot(0, PCI_DEVFN(0x18, 2));
@@ -453,9 +453,15 @@ static void internal_gfx_pci_dev_init(struct device *dev)
        vgainfo.usMinNBVoltage = 0;
        vgainfo.usBootUpNBVoltage = 0x1a;
 
+       /* Get SBLink value (HyperTransport I/O Hub Link ID). */
+       value = pci_read_config32(k8_f0, 0x64);
+       sblk = (value >> 8) & 0x3;
+       printk(BIOS_DEBUG, "SBLINK = %d.\n", sblk);
+
+       /* HT speed */
        value = pci_read_config32(nb_dev, 0xd0);
        printk(BIOS_DEBUG, "NB HT speed = %x.\n", value);
-       value = pci_read_config32(k8_f0, 0x88);
+       value = pci_read_config32(k8_f0, 0x88 + (sblk * 0x20));
        printk(BIOS_DEBUG, "CPU HT speed = %x.\n", value);
        vgainfo.ulHTLinkFreq = 100 * 100; /* set HT speed. */
 
@@ -1214,6 +1220,40 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port)
                printk(BIOS_DEBUG, "device = %x\n", dev->path.pci.devfn >> 3);
                dual_port_configuration(nb_dev, dev);
                break;
+
+       case 2:
+
+               if(is_dev3_present()){
+                       /* step 1, lane reversal (only need if CMOS option is enabled) */
+                       if (cfg->gfx_lane_reversal) {
+                               set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2);
+                               set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 3, 1 << 3);
+                       }
+                       printk(BIOS_DEBUG, "rs780_gfx_init step1.\n");
+                       /* step 1.1, dual-slot gfx configuration (only need if CMOS option is enabled) */
+                       /* AMD calls the configuration CrossFire */
+                       set_nbmisc_enable_bits(nb_dev, 0x0, 0xf << 8, 5 << 8);
+                       printk(BIOS_DEBUG, "rs780_gfx_init step2.\n");
+
+
+                       printk(BIOS_DEBUG, "device = %x\n", dev->path.pci.devfn >> 3);
+                       dual_port_configuration(nb_dev, dev);
+
+               }else{
+                       if (cfg->gfx_lane_reversal) {
+                               set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2);
+                       }
+                       printk(BIOS_DEBUG, "rs780_gfx_init step1.\n");
+                       printk(BIOS_DEBUG, "rs780_gfx_init step2.\n");
+
+                       if((dev->path.pci.devfn >> 3) == 2)
+                               single_port_configuration(nb_dev, dev);
+                       else{
+                               set_nbmisc_enable_bits(nb_dev, 0xc, 0, 0x2 << 2); /* hide the GFX bridge. */
+                               printk(BIOS_DEBUG, "If dev3.., single port. Do nothing.\n");
+                           }
+               }
+
        default:
                printk(BIOS_INFO, "Incorrect configuration of external GFX slot.\n");
                break;