printk_foo -> printk(BIOS_FOO, ...)

[coreboot.git] / src / southbridge / amd / rs690 / rs690_cmn.c

diff --git a/src/southbridge/amd/rs690/rs690_cmn.c b/src/southbridge/amd/rs690/rs690_cmn.c
index b714dc87c5bfd3354bf6a20c410b50a691c1a063..026341394a670cceb887eabd5ececc42453db503 100644 (file)
--- a/src/southbridge/amd/rs690/rs690_cmn.c
+++ b/src/southbridge/amd/rs690/rs690_cmn.c
@@ -49,11 +49,11 @@ static void nb_write_index(device_t dev, u32 index_reg, u32 index, u32 data)
 u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg)
 {
        /*get BAR3 base address for nbcfg0x1c */
-       u32 addr = pci_read_config32(nb_dev, 0x1c);
-       printk_debug("addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary,
-                    dev->path.u.pci.devfn);
+       u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF;
+       printk(BIOS_DEBUG, "addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary,
+                    dev->path.pci.devfn);
        addr |= dev->bus->secondary << 20 |     /* bus num */
-           dev->path.u.pci.devfn << 12 | reg;
+           dev->path.pci.devfn << 12 | reg;
        return *((u32 *) addr);
 }
 
@@ -62,11 +62,11 @@ void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg_pos, u32 mask
        u32 reg_old, reg;
 
        /*get BAR3 base address for nbcfg0x1c */
-       u32 addr = pci_read_config32(nb_dev, 0x1c);
-       /*printk_debug("write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary,
-                    dev->path.u.pci.devfn);*/
+       u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF;
+       /*printk(BIOS_DEBUG, "write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary,
+                    dev->path.pci.devfn);*/
        addr |= dev->bus->secondary << 20 |     /* bus num */
-           dev->path.u.pci.devfn << 12 | reg_pos;
+           dev->path.pci.devfn << 12 | reg_pos;
 
        reg = reg_old = *((u32 *) addr);
        reg &= ~mask;
@@ -253,7 +253,7 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
                mdelay(40);
                udelay(200);
                lc_state = nbpcie_p_read_index(dev, 0xa5);      /* lc_state */
-               printk_debug("PcieLinkTraining port=%x:lc current state=%x\n",
+               printk(BIOS_DEBUG, "PcieLinkTraining port=%x:lc current state=%x\n",
                             port, lc_state);
                current = lc_state & 0x3f;      /* get LC_CURRENT_STATE, bit0-5 */
 
@@ -274,7 +274,7 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
                        reg =
                            pci_ext_read_config32(nb_dev, dev,
                                                  PCIE_VC0_RESOURCE_STATUS);
-                       printk_debug("PcieTrainPort reg=0x%x\n", reg);
+                       printk(BIOS_DEBUG, "PcieTrainPort reg=0x%x\n", reg);
                        /* check bit1 */
                        if (reg & VC_NEGOTIATION_PENDING) {     /* bit1=1 means the link needs to be re-trained. */
                                /* set bit8=1, bit0-2=bit4-6 */
@@ -307,8 +307,10 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
 */
 void rs690_set_tom(device_t nb_dev)
 {
+       extern uint64_t uma_memory_base;
+
        /* set TOM */
-       pci_write_config32(nb_dev, 0x90, uma_memory_start);
-       nbmc_write_index(nb_dev, 0x1e, uma_memory_start);
+       pci_write_config32(nb_dev, 0x90, uma_memory_base);
+       nbmc_write_index(nb_dev, 0x1e, uma_memory_base);
 }