/*
-* This file is part of the LinuxBIOS project.
-*
-* Copyright (C) 2007 Advanced Micro Devices
-*
-* This program is free software; you can redistribute it and/or modify
-* it under the terms of the GNU General Public License version 2 as
-* published by the Free Software Foundation.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License
-* along with this program; if not, write to the Free Software
-* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-*/
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
#include <arch/io.h>
#include <device/device.h>
} else {
/* Reset and disable COM1 */
- printk_err("Not disabling COM1 due to a bug ...\n");
- /* for now, don't do this! */
- return;
msr = rdmsr(MDD_UART1_CONF);
msr.lo = 1; // reset
wrmsr(MDD_UART1_CONF, msr);
/* Disable the IRQ */
msr = rdmsr(MDD_LEG_IO);
- msr.lo |= ~(0xF << 16);
+ msr.lo &= ~(0xF << 16);
wrmsr(MDD_LEG_IO, msr);
}
msr.lo |= sb->com2_irq << 28;
wrmsr(MDD_IRQM_YHIGH, msr);
- /* GPIO3 - UART2_RX */
- /* Set: Output Enable (0x4) */
- outl(GPIOL_3_SET, gpio_addr + GPIOL_OUTPUT_ENABLE);
+ /* GPIO4 - UART2_RX */
+ /* Set: Output Enable (0x4) */
+ outl(GPIOL_4_SET, gpio_addr + GPIOL_OUTPUT_ENABLE);
/* Set: OUTAUX1 Select (0x10) */
- outl(GPIOL_3_SET, gpio_addr + GPIOL_OUT_AUX1_SELECT);
+ outl(GPIOL_4_SET, gpio_addr + GPIOL_OUT_AUX1_SELECT);
- /* GPIO4 - UART2_TX */
- /* Set: Input Enable (0x20) */
- outl(GPIOL_4_SET, gpio_addr + GPIOL_INPUT_ENABLE);
- /* Set: INAUX1 Select (0x34) */
- outl(GPIOL_4_SET, gpio_addr + GPIOL_IN_AUX1_SELECT);
+ /* GPIO3 - UART2_TX */
+ /* Set: Input Enable (0x20) */
+ outl(GPIOL_3_SET, gpio_addr + GPIOL_INPUT_ENABLE);
+ /* Set: INAUX1 Select (0x34) */
+ outl(GPIOL_3_SET, gpio_addr + GPIOL_IN_AUX1_SELECT);
- /* Set: GPIO 3 + 3 Pull Up (0x18) */
+ /* Set: GPIO 3 and 4 Pull Up (0x18) */
outl(GPIOL_3_SET | GPIOL_4_SET,
gpio_addr + GPIOL_PULLUP_ENABLE);
/* Disable the IRQ */
msr = rdmsr(MDD_LEG_IO);
- msr.lo |= ~(0xF << 20);
+ msr.lo &= ~(0xF << 20);
wrmsr(MDD_LEG_IO, msr);
}
}
static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
{
- uint32_t *bar;
+ uint8_t *bar;
msr_t msr;
device_t dev;
/* write to clear diag register */
wrmsr(USB2_SB_GLD_MSR_DIAG, rdmsr(USB2_SB_GLD_MSR_DIAG));
- bar = (uint32_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0);
+ bar = (uint8_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0);
/* Make HCCPARAMS writeable */
- *(bar + IPREG04) |= USB_HCCPW_SET;
+ writel(readl(bar + IPREG04) | USB_HCCPW_SET, bar + IPREG04);
/* ; EECP=50h, IST=01h, ASPC=1 */
- *(bar + HCCPARAMS) = 0x00005012;
+ writel(0x00005012, bar + HCCPARAMS);
}
dev = dev_find_device(PCI_VENDOR_ID_AMD,
PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
if (dev) {
- bar = (uint32_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0);
+ bar = (uint8_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0);
- *(bar + UOCMUX) &= PUEN_SET;
+ writel(readl(bar + UOCMUX) & PUEN_SET, bar + UOCMUX);
/* Host or Device? */
if (sb->enable_USBP4_device) {
- *(bar + UOCMUX) |= PMUX_DEVICE;
+ writel(readl(bar + UOCMUX) | PMUX_DEVICE, bar + UOCMUX);
} else {
- *(bar + UOCMUX) |= PMUX_HOST;
+ writel(readl(bar + UOCMUX) | PMUX_HOST, bar + UOCMUX);
}
/* Overcurrent configuration */
if (sb->enable_USBP4_overcurrent) {
- *(bar + UOCCAP) |= sb->enable_USBP4_overcurrent;
+ writel(readl(bar + UOCCAP)
+ | sb->enable_USBP4_overcurrent, bar + UOCCAP);
}
}
dev = dev_find_device(PCI_VENDOR_ID_AMD,
PCI_DEVICE_ID_AMD_CS5536_UDC, 0);
if (dev) {
- bar = (uint32_t *) pci_read_config32(dev,
+ bar = (uint8_t *) pci_read_config32(dev,
PCI_BASE_ADDRESS_0);
- *(bar + UDCDEVCTL) |= UDC_SD_SET;
+ writel(readl(bar + UDCDEVCTL) | UDC_SD_SET,
+ bar + UDCDEVCTL);
}
dev = dev_find_device(PCI_VENDOR_ID_AMD,
PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
if (dev) {
- bar = (uint32_t *) pci_read_config32(dev,
+ bar = (uint8_t *) pci_read_config32(dev,
PCI_BASE_ADDRESS_0);
- *(bar + UOCCTL) |= PADEN_SET;
- *(bar + UOCCAP) |= APU_SET;
+ writel(readl(bar + UOCCTL) | PADEN_SET, bar + UOCCTL);
+ writel(readl(bar + UOCCAP) | APU_SET, bar + UOCCAP);
}
}
post_code(P80_CHIPSET_INIT);
- /* we hope NEVER to be in linuxbios when S3 resumes
+ /* we hope NEVER to be in coreboot when S3 resumes
if (! IsS3Resume()) */
{
struct acpiinit *aci = acpi_init_table;
.scan_bus = scan_static_bus,
};
-static struct pci_driver cs5536_pci_driver __pci_driver = {
+static const struct pci_driver cs5536_pci_driver __pci_driver = {
.ops = &southbridge_ops,
.vendor = PCI_VENDOR_ID_AMD,
.device = PCI_DEVICE_ID_AMD_CS5536_ISA