cimx_wrapper/sb800: Fix indent in late.c:sb800_enable()

[coreboot.git] / src / southbridge / amd / cimx_wrapper / sb800 / late.c

diff --git a/src/southbridge/amd/cimx_wrapper/sb800/late.c b/src/southbridge/amd/cimx_wrapper/sb800/late.c
index 45689d7627a7faa1c4523ed91856ed5dac23e6df..e375b23dd8e02aebbc2373dc675d110ffc6ee2f3 100644 (file)
--- a/src/southbridge/amd/cimx_wrapper/sb800/late.c
+++ b/src/southbridge/amd/cimx_wrapper/sb800/late.c
@@ -315,7 +315,6 @@ static const struct pci_driver PORTD_driver __pci_driver = {
  */
 static void sb800_enable(device_t dev)
 {
-       u8 gpp_port = 0;
        struct southbridge_amd_cimx_wrapper_sb800_config *sb_chip =
                (struct southbridge_amd_cimx_wrapper_sb800_config *)(dev->chip_info);
 
@@ -352,6 +351,25 @@ static void sb800_enable(device_t dev)
                break;
 
        case (0x14 << 3) | 0: /* 0:14:0 SMBUS */
+        {
+           u8 byte;
+           u32 ioapic_base;
+
+           printk(BIOS_INFO, "sm_init().\n");
+           ioapic_base = 0xFEC00000;
+           clear_ioapic(ioapic_base);
+           /* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */
+           #if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS < 16)
+           /* Assign the ioapic ID the next available number after the processor core local APIC IDs */
+           setup_ioapic(ioapic_base, CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS);
+           #elif (CONFIG_APIC_ID_OFFSET > 0)
+           /* Assign the ioapic ID the value 0. Processor APIC IDs follow. */ 
+           setup_ioapic(ioapic_base, 0);
+           #else
+           #error "The processor APIC IDs must be lifted to make room for the I/O APIC ID"
+           #endif
+        }
+
                break;
 
        case (0x14 << 3) | 1: /* 0:14:1 IDE */
@@ -395,15 +413,16 @@ static void sb800_enable(device_t dev)
                break;
 
        case (0x15 << 3) | 0: /* 0:15:0 PCIe PortA */
+               sb_config->PORTCONFIG[0].PortCfg.PortPresent = dev->enabled;
+               return;
        case (0x15 << 3) | 1: /* 0:15:1 PCIe PortB */
+               sb_config->PORTCONFIG[1].PortCfg.PortPresent = dev->enabled;
+               return;
        case (0x15 << 3) | 2: /* 0:15:2 PCIe PortC */
+               sb_config->PORTCONFIG[2].PortCfg.PortPresent = dev->enabled;
+               return;
        case (0x15 << 3) | 3: /* 0:15:3 PCIe PortD */
-               gpp_port = (dev->path.pci.devfn) & 0x03;
-               if (dev->enabled) {
-                       sb_config->PORTCONFIG[gpp_port].PortCfg.PortPresent = ENABLED;
-               } else {
-                       sb_config->PORTCONFIG[gpp_port].PortCfg.PortPresent = DISABLED;
-               }
+               sb_config->PORTCONFIG[3].PortCfg.PortPresent = dev->enabled;
 
                /*
                 * GPP_CFGMODE_X4000: PortA Lanes[3:0]