Add AMD SB900 CIMx code

[coreboot.git] / src / southbridge / amd / cimx_wrapper / sb800 / bootblock.c

diff --git a/src/southbridge/amd/cimx_wrapper/sb800/bootblock.c b/src/southbridge/amd/cimx_wrapper/sb800/bootblock.c
index a29bf8c3f566503f96732a187ab529f291b1ee77..aaec03cbea4507095f54387c78dca5feac36673c 100644 (file)
--- a/src/southbridge/amd/cimx_wrapper/sb800/bootblock.c
+++ b/src/southbridge/amd/cimx_wrapper/sb800/bootblock.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -20,91 +20,75 @@
 #include <arch/io.h>
 #include <arch/romcc_io.h>
 
-#if CONFIG_SERIAL_POST == 1
-
-/* Data */
-#define UART_RBR 0x00
-#define UART_TBR 0x00
+static void enable_rom(void)
+{
+       u16 word;
+       u32 dword;
+       device_t dev;
 
-/* Control */
-#define UART_IER 0x01
-#define UART_IIR 0x02
-#define UART_FCR 0x02
-#define UART_LCR 0x03
-#define UART_MCR 0x04
-#define UART_DLL 0x00
-#define UART_DLM 0x01
+       dev = PCI_DEV(0, 0x14, 0x03);
+       /* SB800 LPC Bridge 0:20:3:44h.
+        * BIT6: Port Enable for serial port 0x3f8-0x3ff
+        * BIT29: Port Enable for KBC port 0x60 and 0x64
+        * BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62
+        */
+       dword = pci_io_read_config32(dev, 0x44);
+       //dword |= (1<<6) | (1<<29) | (1<<30) ;
+       /* Turn on all of LPC IO Port decode enable */
+       dword = 0xffffffff;
+       pci_io_write_config32(dev, 0x44, dword);
 
-/* Status */
-#define UART_LSR 0x05
-#define UART_MSR 0x06
-#define UART_SCR 0x07
+       /* SB800 LPC Bridge 0:20:3:48h.
+        * BIT0: Port Enable for SuperIO 0x2E-0x2F 
+        * BIT1: Port Enable for SuperIO 0x4E-0x4F 
+        * BIT4: Port Enable for LPC ROM Address Arrage2 (0x68-0x6C)
+        * BIT6: Port Enable for RTC IO 0x70-0x73
+        * BIT21: Port Enable for Port 0x80
+        */
+       dword = pci_io_read_config32(dev, 0x48);
+       dword |= (1 << 0) | (1 << 1) | (1 << 4) | (1 << 6) | (1 << 21);
+       pci_io_write_config32(dev, 0x48, dword);
 
-#ifndef CONFIG_TTYS0_DIV
-#if ((115200%CONFIG_TTYS0_BAUD) != 0)
-#error Bad ttys0 baud rate
-#endif
-#define CONFIG_TTYS0_DIV       (115200/CONFIG_TTYS0_BAUD)
-#endif // CONFIG_TTYS0_DIV
+       /* Enable 4MB rom access at 0xFFE00000 - 0xFFFFFFFF */
+       /* Set the 4MB enable bits */
+       word = pci_io_read_config16(dev, 0x6c);
+       word = 0xFFC0;
+       pci_io_write_config16(dev, 0x6c, word);
+}
 
-#define UART_LCS       CONFIG_TTYS0_LCS
+static void enable_prefetch(void)
+{
+       u32 dword;
+       device_t dev = PCI_DEV(0, 0x14, 0x03);
 
-#endif // CONFIG_SERIAL_POST == 1
+       /* Enable PrefetchEnSPIFromHost */
+       dword = pci_io_read_config32(dev, 0xb8);
+       pci_io_write_config32(dev, 0xb8, dword | (1 << 24));
+}
 
-static void sb800_enable_rom(void)
+static void enable_spi_fast_mode(void)
 {
-  u32 word;
-  u32 dword;
-  device_t dev;
-
-  dev = PCI_DEV(0, 0x14, 0x03);
-  /* SB800 LPC Bridge 0:20:3:44h.
-   * BIT6: Port Enable for serial port 0x3f8-0x3ff
-   * BIT29: Port Enable for KBC port 0x60 and 0x64
-   * BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62
-   */
-  dword = pci_io_read_config32(dev, 0x44);
-  //dword |= (1<<6) | (1<<29) | (1<<30) ;
-  /*Turn on all of LPC IO Port decode enable */
-  dword = 0xffffffff;
-  pci_io_write_config32(dev, 0x44, dword);
+       u8 byte;
+       u32 dword;
+       device_t dev = PCI_DEV(0, 0x14, 0x03);
 
-  /* SB800 LPC Bridge 0:20:3:48h.
-   * BIT0: Port Enable for SuperIO 0x2E-0x2F
-   * BIT1: Port Enable for SuperIO 0x4E-0x4F
-   * BIT4: Port Enable for LPC ROM Address Arrage2 (0x68-0x6C)
-   * BIT6: Port Enable for RTC IO 0x70-0x73
-   * BIT21: Port Enable for Port 0x80
-   */
-  dword = pci_io_read_config32(dev, 0x48);
-  dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21) ;
-  pci_io_write_config32(dev, 0x48, dword);
+       // set temp MMIO base
+       volatile u32 *spi_base = (void *)0xa0000000;
+       u32 save = pci_io_read_config32(dev, 0xa0);
+       pci_io_write_config32(dev, 0xa0, (u32) spi_base | 2);
 
-  /* Enable 2MB rom access at 0xFFE00000 - 0xFFFFFFFF */
-  /* Set the 2MB enable bits */
-  word = pci_io_read_config16(dev, 0x6c);
-  word = 0xFFE0;
-  pci_io_write_config16(dev, 0x6c, word);
-}
+       // early enable of SPI 33 MHz fast mode read
+       byte = spi_base[3];
+       spi_base[3] = (byte & ~(3 << 14)) | (1 << 14);
+       spi_base[0] = spi_base[0] | (1 << 18);  // fast read enable
 
-static void uart_init(void)
-{
-#if CONFIG_SERIAL_POST == 1
-  /* disable interrupts */
-  outb(0x0, CONFIG_TTYS0_BASE + UART_IER);
-  /* enable fifo's */
-  outb(0x01, CONFIG_TTYS0_BASE + UART_FCR);
-  /* Set Baud Rate Divisor to 12 ==> 115200 Baud */
-  outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR);
-  outb(CONFIG_TTYS0_DIV & 0xFF,   CONFIG_TTYS0_BASE + UART_DLL);
-  outb((CONFIG_TTYS0_DIV >> 8) & 0xFF,    CONFIG_TTYS0_BASE + UART_DLM);
-  outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR);
-#endif // CONFIG_SERIAL_POST == 1
+       pci_io_write_config32(dev, 0xa0, save);
 }
 
 static void bootblock_southbridge_init(void)
 {
-  /* Setup the rom access for 2M */
-  sb800_enable_rom();
-  uart_init();
+       /* Setup the rom access for 2M */
+       enable_rom();
+       enable_prefetch();
+       enable_spi_fast_mode();
 }