Persimmon audio codec verb patch.

[coreboot.git] / src / southbridge / amd / cimx / sb800 / cfg.c

diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c
index 57ff7181afbd6f4e9e33e6030940db7de96313e0..a9e35bcb8181850d97c66d0ec075ffe7f7ff8fd1 100644 (file)
--- a/src/southbridge/amd/cimx/sb800/cfg.c
+++ b/src/southbridge/amd/cimx/sb800/cfg.c
@@ -31,10 +31,8 @@
 void sb800_cimx_config(AMDSBCFG *sb_config)
 {
        if (!sb_config) {
-               printk(BIOS_DEBUG, "SB800 - Cfg.c - sb800_cimx_config - No sb_config.\n");
                return;
        }
-       printk(BIOS_INFO, "SB800 - Cfg.c - sb800_cimx_config - Start.\n");
        //memset(sb_config, 0, sizeof(AMDSBCFG));
 
        /* header */
@@ -50,6 +48,7 @@ void sb800_cimx_config(AMDSBCFG *sb_config)
        sb_config->BuildParameters.AcpiPm1CntBlkAddr = PM1_CNT_BLK_ADDRESS;
        sb_config->BuildParameters.AcpiPm1EvtBlkAddr = PM1_EVT_BLK_ADDRESS;
        sb_config->BuildParameters.SioPmeBaseAddress = SIO_PME_BASE_ADDRESS;
+       sb_config->BuildParameters.SioHwmBaseAddress = SIO_HWM_BASE_ADDRESS;
        sb_config->BuildParameters.SpiRomBaseAddress = SPI_BASE_ADDRESS;
        sb_config->BuildParameters.GecShadowRomBase = GEC_BASE_ADDRESS;
        sb_config->BuildParameters.Smbus0BaseAddress = SMBUS0_BASE_ADDRESS;
@@ -85,14 +84,23 @@ void sb800_cimx_config(AMDSBCFG *sb_config)
        sb_config->SATAMODE.SataMode.SataController = SATA_CONTROLLER;
        sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary, 1 -IDE as secondary.
                                                                //TODO: set to secondary not take effect.
-       sb_config->SATAMODE.SataMode.SataIdeCombinedMode = 0; //IDE controlor exposed and combined mode enabled
+       sb_config->SATAMODE.SataMode.SataIdeCombinedMode = CONFIG_IDE_COMBINED_MODE;
        sb_config->SATAMODE.SataMode.SATARefClkSel = SATA_CLOCK_SOURCE;
 
        /* Azalia HDA */
        sb_config->AzaliaController = AZALIA_CONTROLLER;
        sb_config->AzaliaPinCfg = AZALIA_PIN_CONFIG;
        sb_config->AZALIACONFIG.AzaliaSdinPin = AZALIA_SDIN_PIN;
+       /* Mainboard Specific Azalia Cocec Verb Table */
+#ifdef AZALIA_OEM_VERB_TABLE
+       sb_config->AZOEMTBL.pAzaliaOemCodecTablePtr = (CODECTBLLIST *)AZALIA_OEM_VERB_TABLE;
+#else
        sb_config->AZOEMTBL.pAzaliaOemCodecTablePtr = NULL;
+#endif
+
+       /* LPC */
+       /* SuperIO hardware monitor register access */
+       sb_config->SioHwmPortEnable = CONFIG_SB_SUPERIO_HWM;
 
        /*
         * GPP. default configure only enable port0 with 4 lanes,
@@ -105,7 +113,7 @@ void sb800_cimx_config(AMDSBCFG *sb_config)
        sb_config->PORTCONFIG[1].PortCfg.PortPresent = CIMX_OPTION_ENABLED;
        sb_config->PORTCONFIG[2].PortCfg.PortPresent = CIMX_OPTION_ENABLED;
        sb_config->PORTCONFIG[3].PortCfg.PortPresent = CIMX_OPTION_ENABLED;
-       sb_config->GppUnhidePorts = TRUE; //visable always, even port empty
+       sb_config->GppUnhidePorts = SB_GPP_UNHIDE_PORTS;
        sb_config->NbSbGen2 = NB_SB_GEN2;
        sb_config->GppGen2 = SB_GPP_GEN2;
 
@@ -123,6 +131,5 @@ void sb800_cimx_config(AMDSBCFG *sb_config)
                sb_config->StdHeader.CALLBACK.CalloutPtr = sb800_callout_entry;
        }
 #endif //!__PRE_RAM__
-       printk(BIOS_INFO, "SB800 - Cfg.c - sb800_cimx_config - End.\n");
 }