Add constants for fast path resume copying

[coreboot.git] / src / southbridge / amd / cimx / sb800 / Kconfig

diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig
index dc1400f04f384708575f770cd9d7149f5d4e0830..79624e00c474659759dff7e6c3dca64ed524463e 100644 (file)
--- a/src/southbridge/amd/cimx/sb800/Kconfig
+++ b/src/southbridge/amd/cimx/sb800/Kconfig
@@ -19,11 +19,108 @@
 
 config SOUTHBRIDGE_AMD_CIMX_SB800
        bool
+       default n
        select IOAPIC
+       select AMD_SB_CIMX
 
 if SOUTHBRIDGE_AMD_CIMX_SB800
 config BOOTBLOCK_SOUTHBRIDGE_INIT
         string
         default "southbridge/amd/cimx/sb800/bootblock.c"
+
+config ENABLE_IDE_COMBINED_MODE
+       bool "Enable SATA IDE combined mode"
+       default n
+       help
+         If Combined Mode is enabled. IDE controller is exposed and
+         SATA controller has control over Port0 through Port3,
+         IDE controller has control over Port4 and Port5.
+
+         If Combined Mode is disabled, IDE controller is hidden and
+         SATA controller has full control of all 6 Ports when operating in non-IDE mode.
+
+config IDE_COMBINED_MODE
+       hex
+       default "0x0" if ENABLE_IDE_COMBINED_MODE
+       default "0x1" if !ENABLE_IDE_COMBINED_MODE
+
+choice
+       prompt "SATA Mode"
+       default SB800_SATA_IDE
+       help
+         Select the mode in which SATA should be driven. NATIVE AHCI, or RAID.
+         The default is NATIVE.
+
+config SB800_SATA_IDE
+       bool "NATIVE"
+       help
+         NATIVE is the default mode and does not require a ROM.
+
+config SB800_SATA_AHCI
+       bool "AHCI"
+       help
+         AHCI may work with or without AHCI ROM. It depends on the payload support.
+         For example, seabios does not require the AHCI ROM.
+
+config SB800_SATA_RAID
+       bool "RAID"
+       help
+         sb800 RAID mode must have the two required ROM files.
+
+endchoice
+
+config SB800_SATA_MODE
+        hex
+       depends on (SB800_SATA_IDE || SB800_SATA_RAID || SB800_SATA_AHCI)
+       default "0x0" if SB800_SATA_IDE
+       default "0x1" if SB800_SATA_RAID
+       default "0x2" if SB800_SATA_AHCI
+
+config SB_SUPERIO_HWM
+        bool
+        default n
+
+if SB800_SATA_AHCI
+config AHCI_ROM_ID
+       string "AHCI device PCI IDs"
+       default "1002,4391"
+
+config SB800_AHCI_ROM
+       bool "Add a AHCI ROM"
+
+config AHCI_ROM_FILE
+       string "AHCI ROM path and filename"
+       depends on SB800_AHCI_ROM
+       default "site-local/sb800/ahci.bin"
+endif
+
+if SB800_SATA_RAID
+config RAID_ROM_ID
+       string "RAID device PCI IDs"
+       default "1002,4393"
+        help
+          1002,4392 for SATA NON-RAID5 module, 1002,4393 for SATA RAID5 mode
+
+config RAID_ROM_FILE
+       string "RAID ROM path and filename"
+       depends on SB800_SATA_RAID
+       default "site-local/sb800/raid.bin"
+
+config RAID_MISC_ROM_FILE
+        string "RAID Misc ROM path and filename"
+        default "site-local/sb800/misc.bin"
+       depends on SB800_SATA_RAID
+
+config RAID_MISC_ROM_POSITION
+       hex "RAID Misc ROM Position"
+       default 0xFFF00000
+       depends on SB800_SATA_RAID
+       help
+         The RAID ROM requires that the MISC ROM is located between the range
+         0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned.
+         The CONFIG_ROM_SIZE must larger than 0x100000.
+
+endif
+
 endif #SOUTHBRIDGE_AMD_CIMX_SB800