Add constants for fast path resume copying

[coreboot.git] / src / southbridge / amd / cimx / sb800 / Kconfig

diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig
index b7ac0dbf0281d94ae3919802cb24d435b105027d..79624e00c474659759dff7e6c3dca64ed524463e 100644 (file)
--- a/src/southbridge/amd/cimx/sb800/Kconfig
+++ b/src/southbridge/amd/cimx/sb800/Kconfig
@@ -28,6 +28,22 @@ config BOOTBLOCK_SOUTHBRIDGE_INIT
         string
         default "southbridge/amd/cimx/sb800/bootblock.c"
 
+config ENABLE_IDE_COMBINED_MODE
+       bool "Enable SATA IDE combined mode"
+       default n
+       help
+         If Combined Mode is enabled. IDE controller is exposed and
+         SATA controller has control over Port0 through Port3,
+         IDE controller has control over Port4 and Port5.
+
+         If Combined Mode is disabled, IDE controller is hidden and
+         SATA controller has full control of all 6 Ports when operating in non-IDE mode.
+
+config IDE_COMBINED_MODE
+       hex
+       default "0x0" if ENABLE_IDE_COMBINED_MODE
+       default "0x1" if !ENABLE_IDE_COMBINED_MODE
+
 choice
        prompt "SATA Mode"
        default SB800_SATA_IDE
@@ -95,6 +111,15 @@ config RAID_MISC_ROM_FILE
         default "site-local/sb800/misc.bin"
        depends on SB800_SATA_RAID
 
+config RAID_MISC_ROM_POSITION
+       hex "RAID Misc ROM Position"
+       default 0xFFF00000
+       depends on SB800_SATA_RAID
+       help
+         The RAID ROM requires that the MISC ROM is located between the range
+         0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned.
+         The CONFIG_ROM_SIZE must larger than 0x100000.
+
 endif
 
 endif #SOUTHBRIDGE_AMD_CIMX_SB800