Since some people disapprove of white space cleanups mixed in regular commits

[coreboot.git] / src / southbridge / amd / amd8151 / amd8151_agp3.c

diff --git a/src/southbridge/amd/amd8151/amd8151_agp3.c b/src/southbridge/amd/amd8151/amd8151_agp3.c
index b7862feff95d87ba5c7c10cb82e24e31fe2b5118..5d673f6ae8c986c98c1dc5d03a297b8a80064c62 100644 (file)
--- a/src/southbridge/amd/amd8151/amd8151_agp3.c
+++ b/src/southbridge/amd/amd8151/amd8151_agp3.c
@@ -11,65 +11,65 @@
 
 static void agp3bridge_init(device_t dev)
 {
-       uint32_t dword;
-       
-       dword = pci_read_config8(dev, 0x04);
-        dword |= 0x07;
-        pci_write_config8(dev, 0x04, dword);
-       
+       uint8_t byte;
+
+       /* Enable BM, MEM and IO */
+       byte = pci_read_config32(dev, 0x04);
+       byte |= 0x07;
+       pci_write_config8(dev, 0x04, byte);
+
        return;
 }
 
 static struct device_operations agp3bridge_ops  = {
-        .read_resources = pci_bus_read_resources,
-        .set_resources = pci_dev_set_resources,
-        .init = agp3bridge_init,
-        .scan_bus = pci_scan_bridge,
+       .read_resources   = pci_bus_read_resources,
+       .set_resources    = pci_dev_set_resources,
+       .enable_resources = pci_bus_enable_resources,
+       .init             = agp3bridge_init,
+       .scan_bus         = pci_scan_bridge,
 };
 
-static struct pci_driver agp3bridge_driver __pci_driver = {
-        .ops    = &agp3bridge_ops,
-        .vendor = PCI_VENDOR_ID_AMD,
-        .device = 0x7455,
+static const struct pci_driver agp3bridge_driver __pci_driver = {
+       .ops    = &agp3bridge_ops,
+       .vendor = PCI_VENDOR_ID_AMD,
+       .device = 0x7455, // AGP Bridge
 };
 
-
 static void agp3dev_enable(device_t dev)
 {
        uint32_t value;
-       
-       //  AGP enable
-        value = pci_read_config32(dev, 0xa8);
-        value |= (1<<8);
-        pci_write_config32(dev, 0xa8, value);
 
-       //  linkA 8bit-->16bit
-        value = pci_read_config32(dev, 0xc4);
-        value |= (11<<24);
-        pci_write_config32(dev, 0xc4, value);
+       /* AGP enable */
+       value = pci_read_config32(dev, 0xa8);
+       value |= (3<<8)|2; //AGP 8x
+       pci_write_config32(dev, 0xa8, value);
 
-        //  linkA 200-->600
-        value = pci_read_config32(dev, 0xcc);
-        value |= (4<<8);
-        pci_write_config32(dev, 0xcc, value);
-  
-
-        value = pci_read_config32(dev, 0x4);
-        value |= 6;
-        pci_write_config32(dev, 0x4, value);
+       /* enable BM and MEM */
+       value = pci_read_config32(dev, 0x4);
+       value |= 6;
+       pci_write_config32(dev, 0x4, value);
+#if 0
+       /* FIXME: should we add agp aperture base and size here ?
+        * or it is done by AGP drivers */
+#endif
 }
 
+static struct pci_operations pci_ops_pci_dev = {
+        .set_subsystem    = pci_dev_set_subsystem,
+};
+
 static struct device_operations agp3dev_ops = {
-       .read_resources = pci_dev_read_resources,
-       .set_resources  = pci_dev_set_resources,
+       .read_resources   = pci_dev_read_resources,
+       .set_resources    = pci_dev_set_resources,
+       .enable_resources = pci_dev_enable_resources,
        .init     = 0,
        .scan_bus = 0,
        .enable   = agp3dev_enable,
+       .ops_pci  = &pci_ops_pci_dev,
 };
 
-static struct pci_driver agp3dev_driver __pci_driver = {
+static const struct pci_driver agp3dev_driver __pci_driver = {
        .ops    = &agp3dev_ops,
        .vendor = PCI_VENDOR_ID_AMD,
-       .device = 0x7454,
-       
+       .device = 0x7454, //AGP Device
 };