printk_foo -> printk(BIOS_FOO, ...)

[coreboot.git] / src / southbridge / amd / amd8131 / amd8131_bridge.c

diff --git a/src/southbridge/amd/amd8131/amd8131_bridge.c b/src/southbridge/amd/amd8131/amd8131_bridge.c
index 828b083f2e96df4581a50d995a92d4191fbf3498..04930517e681bc7d1ca4207b0f90bd8057c9cf78 100644 (file)
--- a/src/southbridge/amd/amd8131/amd8131_bridge.c
+++ b/src/southbridge/amd/amd8131/amd8131_bridge.c
@@ -46,8 +46,8 @@ static void amd8131_count_dev(device_t dev, void *ptr)
        if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE) {
                info->master_devices++;
        }
-       if (PCI_FUNC(dev->path.u.pci.devfn) > info->max_func) {
-               info->max_func = PCI_FUNC(dev->path.u.pci.devfn);
+       if (PCI_FUNC(dev->path.pci.devfn) > info->max_func) {
+               info->max_func = PCI_FUNC(dev->path.pci.devfn);
        }
 }
 
@@ -76,14 +76,14 @@ static void amd8131_pcix_tune_dev(device_t dev, void *ptr)
                if (sib == dev) {
                        continue;
                }
-               if (PCI_SLOT(sib->path.u.pci.devfn) != PCI_SLOT(dev->path.u.pci.devfn)) {
+               if (PCI_SLOT(sib->path.pci.devfn) != PCI_SLOT(dev->path.pci.devfn)) {
                        continue;
                }
                sib_funcs++;
        }
 
 
-       printk_debug("%s AMD8131 PCI-X tuning\n", dev_path(dev));
+       printk(BIOS_DEBUG, "%s AMD8131 PCI-X tuning\n", dev_path(dev));
        status = pci_read_config32(dev, cap + PCI_X_STATUS);
        orig_cmd = cmd = pci_read_config16(dev,cap + PCI_X_CMD);
 
@@ -170,7 +170,7 @@ static void amd8131_pcix_tune_dev(device_t dev, void *ptr)
                }
        }
 #if 0
-       printk_debug("%s max_read: %d max_tran: %d sibs: %d sib_funcs: %d\n",
+       printk(BIOS_DEBUG, "%s max_read: %d max_tran: %d sibs: %d sib_funcs: %d\n",
                dev_path(dev), max_read, max_tran, sibs, sib_funcs, sib_funcs);
 #endif
        if (max_read != ((cmd & PCI_X_CMD_MAX_READ) >> 2)) {
@@ -214,7 +214,7 @@ static unsigned int amd8131_scan_bus(struct bus *bus,
        info.sstatus = pci_read_config16(bus->dev, pos + PCI_X_SEC_STATUS);
 
        /* Print the PCI-X bus speed */
-       printk_debug("PCI: %02x: %s\n", bus->secondary, pcix_speed(info.sstatus));
+       printk(BIOS_DEBUG, "PCI: %02x: %s\n", bus->secondary, pcix_speed(info.sstatus));
 
 
        /* Examine the bus and find out how loaded it is */
@@ -260,7 +260,7 @@ static unsigned int amd8131_scan_bus(struct bus *bus,
         * implement relaxed ordering.  Errata #58
         */
        for(pbus = bus; !pbus->disable_relaxed_ordering; pbus = pbus->dev->bus) {
-               printk_spew("%s disabling relaxed ordering\n",
+               printk(BIOS_SPEW, "%s disabling relaxed ordering\n",
                        bus_path(pbus));
                pbus->disable_relaxed_ordering = 1;
        }
@@ -364,9 +364,6 @@ static void bridge_set_resources(struct device *dev)
                /* set the memory range */
                dev->command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
                res->flags |= IORESOURCE_STORED;
-               compute_allocate_resource(&dev->link[0], res,
-                       IORESOURCE_MEM | IORESOURCE_PREFETCH,
-                       IORESOURCE_MEM);
                base = res->base;
                end  = resource_end(res);
                pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16);
@@ -394,7 +391,7 @@ static struct device_operations pcix_ops  = {
        .reset_bus        = pci_bus_reset,
 };
 
-static struct pci_driver pcix_driver __pci_driver = {
+static const struct pci_driver pcix_driver __pci_driver = {
         .ops    = &pcix_ops,
         .vendor = PCI_VENDOR_ID_AMD,
         .device = 0x7450,
@@ -427,7 +424,7 @@ static struct device_operations ioapic_ops = {
        .ops_pci          = &pci_ops_pci_dev,
 };
 
-static struct pci_driver ioapic_driver __pci_driver = {
+static const struct pci_driver ioapic_driver __pci_driver = {
        .ops    = &ioapic_ops,
        .vendor = PCI_VENDOR_ID_AMD,
        .device = 0x7451,