Rename the apm, pcibios, and elf entry points.

[seabios.git] / src / smp.c

diff --git a/src/smp.c b/src/smp.c
index 71004767ba5c23f0ebba65c54d045cf4105f3b6d..40f5451e5fee4ec0276de4a8c5203467892120ae 100644 (file)
--- a/src/smp.c
+++ b/src/smp.c
@@ -8,7 +8,6 @@
 #include "util.h" // dprintf
 #include "config.h" // CONFIG_*
 #include "cmos.h" // CMOS_BIOS_SMP_COUNT
-#include "farptr.h" // ASSERT32
 #include "paravirt.h"
 
 #define APIC_ICR_LOW ((u8*)BUILD_APIC_ADDR + 0x300)
@@ -35,7 +34,7 @@ wrmsr_smp(u32 index, u64 val)
 
 u32 CountCPUs VAR16VISIBLE;
 u32 MaxCountCPUs VAR16VISIBLE;
-extern void smp_ap_boot_code();
+extern void smp_ap_boot_code(void);
 ASM16(
     "  .global smp_ap_boot_code\n"
     "smp_ap_boot_code:\n"
@@ -70,12 +69,14 @@ ASM16(
 void
 smp_probe(void)
 {
-    ASSERT32();
+    ASSERT32FLAT();
     u32 eax, ebx, ecx, cpuid_features;
     cpuid(1, &eax, &ebx, &ecx, &cpuid_features);
-    if (! (cpuid_features & CPUID_APIC)) {
+    if (eax < 1 || !(cpuid_features & CPUID_APIC)) {
         // No apic - only the main cpu is present.
+        dprintf(1, "No apic - only the main cpu is present.\n");
         CountCPUs= 1;
+        MaxCountCPUs = 1;
         return;
     }
 
@@ -102,6 +103,7 @@ smp_probe(void)
     }
 
     // broadcast SIPI
+    barrier();
     writel(APIC_ICR_LOW, 0x000C4500);
     u32 sipi_vector = BUILD_AP_BOOT_ADDR >> 12;
     writel(APIC_ICR_LOW, 0x000C4600 | sipi_vector);
@@ -112,7 +114,7 @@ smp_probe(void)
     } else {
         u8 cmos_smp_count = inb_cmos(CMOS_BIOS_SMP_COUNT);
         while (cmos_smp_count + 1 != readl(&CountCPUs))
-             ;
+            yield();
     }
 
     // Restore memory.
@@ -125,11 +127,3 @@ smp_probe(void)
     dprintf(1, "Found %d cpu(s) max supported %d cpu(s)\n", readl(&CountCPUs),
         MaxCountCPUs);
 }
-
-// Reset variables to zero
-void
-smp_probe_setup(void)
-{
-    CountCPUs = 0;
-    smp_mtrr_count = 0;
-}