alu: bessere find_msb, von 1295 auf 1054 logic cells (fuer alu)

[hwmod.git] / src / scanner.vhd

diff --git a/src/scanner.vhd b/src/scanner.vhd
index 9e1f0bde5b9e8e28fc8e657d587980fa3d0dd2a9..875cddda4a88fa9979823c6bba6e46ceb2ae9f73 100644 (file)
--- a/src/scanner.vhd
+++ b/src/scanner.vhd
@@ -23,12 +23,13 @@ entity scanner is
 end entity scanner;
 
 architecture beh of scanner is
-       type SCANNER_STATE is (SIDLE, SREAD, SMOD, STAKE, SDEL, SENTER);
+       type SCANNER_STATE is (SINIT, SIDLE, SREAD, STAKE, SDEL, SENTER);
        signal state_int, state_next : SCANNER_STATE;
        signal s_char_int, s_char_next : hbyte;
        signal s_take_int, s_take_next : std_logic;
        signal s_backspace_int, s_backspace_next : std_logic;
        signal do_it_int, do_it_next : std_logic;
+       signal was_f0_int, was_f0_next : std_logic;
 begin
        s_char <= s_char_int;
        s_take <= s_take_int;
@@ -39,7 +40,8 @@ begin
        begin
                if sys_res_n = '0' then
                        -- internal
-                       state_int <= SIDLE;
+                       state_int <= SINIT;
+                       was_f0_int <= '0';
                        -- out
                        s_char_int <= (others => '0');
                        s_take_int <= '0';
@@ -48,6 +50,7 @@ begin
                elsif rising_edge(sys_clk) then
                        -- internal
                        state_int <= state_next;
+                       was_f0_int <= was_f0_next;
                        -- out
                        s_char_int <= s_char_next;
                        s_take_int <= s_take_next;
@@ -57,37 +60,28 @@ begin
        end process;
 
        -- next state
-       process(state_int, new_data, data, finished, s_done)
+       process(state_int, new_data, data, finished, s_done, was_f0_int)
        begin
                state_next <= state_int;
 
                case state_int is
+                       when SINIT =>
+                               state_next <= SIDLE;
                        when SIDLE =>
-                               if new_data = '1' and finished = '0' and s_done = '0' then
+                               if new_data = '1' and was_f0_int = '1' then
                                        state_next <= SREAD;
                                end if;
                        when SREAD =>
                                case data is
-                                       when x"e0" => state_next <= SMOD;
                                        when SC_BKSP => state_next <= SDEL;
                                        when SC_ENTER => state_next <= SENTER;
                                        when SC_KP_0 | SC_KP_1 | SC_KP_2 | SC_KP_3 |
                                                SC_KP_4 | SC_KP_5 | SC_KP_6 | SC_KP_7 |
                                                SC_KP_8 | SC_KP_9 | SC_KP_PLUS |
-                                               SC_KP_MINUS | SC_KP_MUL | SC_SPACE =>
-                                                       state_next <= STAKE;
+                                               SC_KP_MINUS | SC_KP_MUL | SC_SPACE |
+                                               SC_KP_DIV => state_next <= STAKE;
                                        when others => state_next <= SIDLE;
                                end case;
-                       when SMOD =>
-                               if new_data = '1' then
-                                       if data = SC_KP_ENTER then
-                                               state_next <= SENTER;
-                                       elsif data = SC_KP_DIV then
-                                               state_next <= STAKE;
-                                       else
-                                               state_next <= SIDLE;
-                                       end if;
-                               end if;
                        when STAKE | SDEL=>
                                if s_done = '1' then
                                        state_next <= SIDLE;
@@ -100,7 +94,7 @@ begin
        end process;
 
        -- out
-       process(state_int, data)
+       process(state_int, data, s_char_int, new_data, was_f0_int)
                function sc2ascii (x : hbyte) return hbyte is
                        variable y : hbyte;
                begin
@@ -125,18 +119,21 @@ begin
                        return y;
                end function;
        begin
-               s_char_next <= (others => '0');
+               s_char_next <= s_char_int;
                s_take_next <= '0';
                s_backspace_next <= '0';
                do_it_next <= '0';
+               was_f0_next <= was_f0_int;
 
                case state_int is
+                       when SINIT =>
+                               was_f0_next <= '0';
                        when SIDLE =>
-                               null;
+                               if new_data = '1' and data = x"f0" then
+                                       was_f0_next <= '1';
+                               end if;
                        when SREAD =>
-                               null;
-                       when SMOD =>
-                               null;
+                               was_f0_next <= '0';
                        when STAKE =>
                                s_take_next <= '1';
                                s_char_next <= sc2ascii(hbyte(data));