uart_rx: bitorder fail

[hwmod.git] / src / scanner.vhd

diff --git a/src/scanner.vhd b/src/scanner.vhd
index 1710dc437888bae405c9fe804fcf1827ae4f450d..018677c58b8e581d51992ce8bbe2a22b0fd43d25 100644 (file)
--- a/src/scanner.vhd
+++ b/src/scanner.vhd
@@ -18,22 +18,33 @@ entity scanner is
                s_backspace : out std_logic;
                -- Parser
                do_it : out std_logic;
-               finished : in std_logic
+               finished : in std_logic;
+               -- test: uart-tx
+               tx_data : out std_logic_vector(7 downto 0);
+               tx_new : out std_logic;
+               -- test: uart_rx
+               rx_data : in std_logic_vector(7 downto 0);
+               rx_new : in std_logic
        );
 end entity scanner;
 
 architecture beh of scanner is
-       type SCANNER_STATE is (SIDLE, SIGNORE_NEXT, SREAD_NEXT, STAKE, SDEL, SENTER);
+       type SCANNER_STATE is (SIDLE, SIGNORE_NEXT, SREAD_NEXT, STAKE, SDEL, SENTER,
+               STAKE_RS232);
        signal state_int, state_next : SCANNER_STATE;
        signal s_char_int, s_char_next : hbyte;
        signal s_take_int, s_take_next : std_logic;
        signal s_backspace_int, s_backspace_next : std_logic;
        signal do_it_int, do_it_next : std_logic;
+       signal tx_data_int, tx_data_next : std_logic_vector(7 downto 0);
+       signal tx_new_int, tx_new_next : std_logic;
 begin
        s_char <= s_char_int;
        s_take <= s_take_int;
        s_backspace <= s_backspace_int;
        do_it <= do_it_int;
+       tx_new <= tx_new_int;
+       tx_data <= tx_data_int;
 
        process(sys_clk, sys_res_n)
        begin
@@ -45,6 +56,8 @@ begin
                        s_take_int <= '0';
                        s_backspace_int <= '0';
                        do_it_int <= '0';
+                       tx_new_int <= '0';
+                       tx_data_int <= (others => '0');
                elsif rising_edge(sys_clk) then
                        -- internal
                        state_int <= state_next;
@@ -53,13 +66,17 @@ begin
                        s_take_int <= s_take_next;
                        s_backspace_int <= s_backspace_next;
                        do_it_int <= do_it_next;
+                       tx_new_int <= tx_new_next;
+                       tx_data_int <= tx_data_next;
                end if;
        end process;
 
        -- next state
-       process(state_int, new_data, data, finished, s_done)
+       process(state_int, new_data, data, finished, s_done, tx_data_int)
        begin
                state_next <= state_int;
+               tx_new_next <= '0';
+               tx_data_next <= tx_data_int;
 
                case state_int is
                        when SIDLE =>
@@ -84,6 +101,9 @@ begin
                                                when others => state_next <= SIDLE;
                                        end case;
                                end if;
+                               if rx_new = '1' then
+                                       state_next <= STAKE_RS232;
+                               end if;
                        when SIGNORE_NEXT =>
                                if new_data = '1' then
                                        state_next <= SIDLE;
@@ -100,19 +120,21 @@ begin
                                                when others => state_next <= SIDLE;
                                        end case;
                                end if;
-                       when STAKE | SDEL=>
+                       when STAKE | SDEL | STAKE_RS232=>
                                if s_done = '1' then
                                        state_next <= SIDLE;
                                end if;
                        when SENTER =>
                                if finished = '1' then
+                                       tx_new_next <= '1';
+                                       tx_data_next <= x"42";
                                        state_next <= SIDLE;
                                end if;
                end case;
        end process;
 
        -- out
-       process(state_int, data, s_char_int, new_data)
+       process(state_int, data, s_char_int, new_data, rx_data)
                function sc2ascii (x : hbyte) return hbyte is
                        variable y : hbyte;
                begin
@@ -149,6 +171,13 @@ begin
                        when STAKE =>
                                s_take_next <= '1';
                                s_char_next <= sc2ascii(hbyte(data));
+                       when STAKE_RS232 =>
+                               s_take_next <= '1';
+                               if rx_data >= x"30" and rx_data <= x"39" then
+                                       s_char_next <= hbyte(rx_data);
+                               else
+                                       s_char_next <= x"41";
+                               end if;
                        when SDEL =>
                                s_take_next <= '1';
                                s_backspace_next <= '1';