/////////////////////////////////////////////////////////////////////////
-// $Id: rombios32.c,v 1.22 2008/01/27 17:57:26 sshwarts Exp $
-/////////////////////////////////////////////////////////////////////////
//
// 32 bit Bochs BIOS init code
// Copyright (C) 2006 Fabrice Bellard
// License along with this library; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-#include "util.h" // BX_INFO
-#include "cmos.h" // inb_cmos
+#include "util.h" // dprintf
#include "pci.h" // PCIDevice
#include "types.h" // u32
-
-#define BX_APPNAME "Bochs"
-
-#define ACPI_DATA_SIZE 0x00010000L
-#define PM_IO_BASE 0xb000
-#define SMB_IO_BASE 0xb100
-#define CPU_COUNT_ADDR 0xf000
-
-/* if true, put the MP float table and ACPI RSDT in EBDA and the MP
- table in RAM. Unfortunately, Linux has bugs with that, so we prefer
- to modify the BIOS in shadow RAM */
-//#define BX_USE_EBDA_TABLES
-
-/* define it if the (emulated) hardware supports SMM mode */
-#define BX_USE_SMM
+#include "config.h" // CONFIG_*
+#include "memmap.h" // bios_table_cur_addr
+#include "acpi.h" // acpi_bios_init
#define cpuid(index, eax, ebx, ecx, edx) \
asm volatile ("cpuid" \
: "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) \
: "0" (index))
-#define wbinvd() asm volatile("wbinvd")
-
#define CPUID_APIC (1 << 9)
#define APIC_BASE ((u8 *)0xfee00000)
#define APIC_ENABLED 0x0100
-#define AP_BOOT_ADDR 0x10000
-
#define MPTABLE_MAX_SIZE 0x00002000
-#define SMI_CMD_IO_ADDR 0xb2
-
-#define BIOS_TMP_STORAGE 0x00030000 /* 64 KB used to copy the BIOS to shadow RAM */
static inline void writel(void *addr, u32 val)
{
u32 cpuid_signature;
u32 cpuid_features;
u32 cpuid_ext_features;
-unsigned long ram_size;
u8 bios_uuid[16];
-#ifdef BX_USE_EBDA_TABLES
+#if (CONFIG_USE_EBDA_TABLES == 1)
unsigned long ebda_cur_addr;
#endif
-int acpi_enabled;
-u32 pm_io_base, smb_io_base;
-int pm_sci_int;
-unsigned long bios_table_cur_addr;
-unsigned long bios_table_end_addr;
void uuid_probe(void)
{
-#ifdef BX_QEMU
+#if (CONFIG_QEMU == 1)
u32 eax, ebx, ecx, edx;
// check if backdoor port exists
cpuid_ext_features = ecx;
}
-void ram_probe(void)
-{
- if (inb_cmos(0x34) | inb_cmos(0x35))
- ram_size = (inb_cmos(0x34) | (inb_cmos(0x35) << 8)) * 65536 +
- 16 * 1024 * 1024;
- else
- ram_size = (inb_cmos(0x17) | (inb_cmos(0x18) << 8)) * 1024;
-#ifdef BX_USE_EBDA_TABLES
- ebda_cur_addr = ((*(u16 *)(0x40e)) << 4) + 0x380;
-#endif
- BX_INFO("ram_size=0x%08lx\n", ram_size);
-}
-
/****************************************************/
/* SMP probe */
val |= APIC_ENABLED;
writel(APIC_BASE + APIC_SVR, val);
- writew((void *)CPU_COUNT_ADDR, 1);
+ writew((void *)BUILD_CPU_COUNT_ADDR, 1);
/* copy AP boot code */
- memcpy((void *)AP_BOOT_ADDR, &smp_ap_boot_code_start,
+ memcpy((void *)BUILD_AP_BOOT_ADDR, &smp_ap_boot_code_start,
&smp_ap_boot_code_end - &smp_ap_boot_code_start);
/* broadcast SIPI */
writel(APIC_BASE + APIC_ICR_LOW, 0x000C4500);
- sipi_vector = AP_BOOT_ADDR >> 12;
+ sipi_vector = BUILD_AP_BOOT_ADDR >> 12;
writel(APIC_BASE + APIC_ICR_LOW, 0x000C4600 | sipi_vector);
usleep(10*1000);
- smp_cpus = readw((void *)CPU_COUNT_ADDR);
+ smp_cpus = readw((void *)BUILD_CPU_COUNT_ADDR);
}
- BX_INFO("Found %d cpu(s)\n", smp_cpus);
+ dprintf(1, "Found %d cpu(s)\n", smp_cpus);
}
/****************************************************/
#define PCI_DEVICES_MAX 64
-#define PCI_VENDOR_ID 0x00 /* 16 bits */
-#define PCI_DEVICE_ID 0x02 /* 16 bits */
-#define PCI_COMMAND 0x04 /* 16 bits */
-#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
-#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
-#define PCI_CLASS_DEVICE 0x0a /* Device class */
-#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
-#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
-#define PCI_MIN_GNT 0x3e /* 8 bits */
-#define PCI_MAX_LAT 0x3f /* 8 bits */
-
static u32 pci_bios_io_addr;
static u32 pci_bios_mem_addr;
static u32 pci_bios_bigmem_addr;
static u8 pci_irqs[4] = { 11, 9, 11, 9 };
static PCIDevice i440_pcidev;
-static void pci_set_io_region_addr(PCIDevice *d, int region_num, u32 addr)
+static void pci_set_io_region_addr(PCIDevice d, int region_num, u32 addr)
{
u16 cmd;
u32 ofs, old_addr;
old_addr = pci_config_readl(d, ofs);
pci_config_writel(d, ofs, addr);
- BX_INFO("region %d: 0x%08x\n", region_num, addr);
+ dprintf(1, "region %d: 0x%08x\n", region_num, addr);
/* enable memory mappings */
cmd = pci_config_readw(d, PCI_COMMAND);
/* return the global irq number corresponding to a given device irq
pin. We could also use the bus number to have a more precise
mapping. */
-static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
+static int pci_slot_get_pirq(PCIDevice pci_dev, int irq_num)
{
int slot_addend;
- slot_addend = (pci_dev->devfn >> 3) - 1;
+ slot_addend = (pci_dev.devfn >> 3) - 1;
return (irq_num + slot_addend) & 3;
}
-static void
-copy_bios(PCIDevice *d, int v)
-{
- pci_config_writeb(d, 0x59, v);
- memcpy((void *)0x000f0000, (void *)BIOS_TMP_STORAGE, 0x10000);
-}
-
-// Test if 'addr' is in the range from 'start'..'start+size'
-#define IN_RANGE(addr, start, size) ({ \
- u32 __addr = (addr); \
- u32 __start = (start); \
- u32 __size = (size); \
- (__addr - __start < __size); \
- })
-
-static void bios_shadow_init(PCIDevice *d)
-{
- bios_table_cur_addr = 0xf0000 | OFFSET_freespace2_start;
- bios_table_end_addr = 0xf0000 | OFFSET_freespace2_end;
- BX_INFO("bios_table_addr: 0x%08lx end=0x%08lx\n",
- bios_table_cur_addr, bios_table_end_addr);
-
- /* remap the BIOS to shadow RAM an keep it read/write while we
- are writing tables */
- int v = pci_config_readb(d, 0x59);
- v &= 0xcf;
- pci_config_writeb(d, 0x59, v);
- memcpy((void *)BIOS_TMP_STORAGE, (void *)0x000f0000, 0x10000);
- v |= 0x30;
-
- if (IN_RANGE((u32)copy_bios, 0xf0000, 0x10000)) {
- // Current code is in shadowed area. Perform the copy from
- // the code that is in the temporary location.
- u32 pos = (u32)copy_bios - 0xf0000 + BIOS_TMP_STORAGE;
- void (*func)(PCIDevice *, int) = (void*)pos;
- func(d, v);
- } else {
- copy_bios(d, v);
- }
-
- // Clear the area just copied.
- memcpy((void *)BIOS_TMP_STORAGE, 0, 0x10000);
-
- i440_pcidev = *d;
-}
-
-static void bios_lock_shadow_ram(void)
-{
- PCIDevice *d = &i440_pcidev;
- int v;
-
- wbinvd();
- v = pci_config_readb(d, 0x59);
- v = (v & 0x0f) | (0x10);
- pci_config_writeb(d, 0x59, v);
-}
-
-static void pci_bios_init_bridges(PCIDevice *d)
+static void pci_bios_init_bridges(PCIDevice d)
{
u16 vendor_id, device_id;
}
outb(elcr[0], 0x4d0);
outb(elcr[1], 0x4d1);
- BX_INFO("PIIX3 init: elcr=%02x %02x\n",
+ dprintf(1, "PIIX3 init: elcr=%02x %02x\n",
elcr[0], elcr[1]);
} else if (vendor_id == 0x8086 && device_id == 0x1237) {
/* i440 PCI bridge */
- bios_shadow_init(d);
+ i440_pcidev = d;
}
}
"smp_ap_boot_code_start:\n"
" xor %ax, %ax\n"
" mov %ax, %ds\n"
- " incw " __stringify(CPU_COUNT_ADDR) "\n"
+ " incw " __stringify(BUILD_CPU_COUNT_ADDR) "\n"
"1:\n"
" hlt\n"
" jmp 1b\n"
" jne 1f\n"
/* ACPI disable */
- " mov $" __stringify(PM_IO_BASE) " + 0x04, %dx\n" /* PMCNTRL */
+ " mov $" __stringify(BUILD_PM_IO_BASE) " + 0x04, %dx\n" /* PMCNTRL */
" inw %dx, %ax\n"
" andw $~1, %ax\n"
" outw %ax, %dx\n"
" jne 2f\n"
/* ACPI enable */
- " mov $" __stringify(PM_IO_BASE) " + 0x04, %dx\n" /* PMCNTRL */
+ " mov $" __stringify(BUILD_PM_IO_BASE) " + 0x04, %dx\n" /* PMCNTRL */
" inw %dx, %ax\n"
" orw $1, %ax\n"
" outw %ax, %dx\n"
extern u8 smm_relocation_start, smm_relocation_end;
extern u8 smm_code_start, smm_code_end;
-#ifdef BX_USE_SMM
-static void smm_init(PCIDevice *d)
+#if (CONFIG_USE_SMM == 1)
+static void smm_init(PCIDevice d)
{
u32 value;
outb(0x00, 0xb2);
/* wait until SMM code executed */
- while (inb(0xb3) != 0x00);
+ while (inb(0xb3) != 0x00)
+ ;
/* enable the SMM memory window */
- pci_config_writeb(&i440_pcidev, 0x72, 0x02 | 0x48);
+ pci_config_writeb(i440_pcidev, 0x72, 0x02 | 0x48);
/* copy the SMM code */
memcpy((void *)0xa8000, &smm_code_start,
wbinvd();
/* close the SMM memory window and enable normal SMM */
- pci_config_writeb(&i440_pcidev, 0x72, 0x02 | 0x08);
+ pci_config_writeb(i440_pcidev, 0x72, 0x02 | 0x08);
}
}
#endif
-static void pci_bios_init_device(PCIDevice *d)
+static void pci_bios_init_device(PCIDevice d)
{
int class;
u32 *paddr;
class = pci_config_readw(d, PCI_CLASS_DEVICE);
vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
device_id = pci_config_readw(d, PCI_DEVICE_ID);
- BX_INFO("PCI: bus=%d devfn=0x%02x: vendor_id=0x%04x device_id=0x%04x\n",
- d->bus, d->devfn, vendor_id, device_id);
+ dprintf(1, "PCI: bus=%d devfn=0x%02x: vendor_id=0x%04x device_id=0x%04x\n",
+ d.bus, d.devfn, vendor_id, device_id);
switch(class) {
case 0x0101:
if (vendor_id == 0x8086 && device_id == 0x7010) {
if (vendor_id == 0x8086 && device_id == 0x7113) {
/* PIIX4 Power Management device (for ACPI) */
- pm_io_base = PM_IO_BASE;
+ u32 pm_io_base = BUILD_PM_IO_BASE;
pci_config_writel(d, 0x40, pm_io_base | 1);
pci_config_writeb(d, 0x80, 0x01); /* enable PM io space */
- smb_io_base = SMB_IO_BASE;
+ u32 smb_io_base = BUILD_SMB_IO_BASE;
pci_config_writel(d, 0x90, smb_io_base | 1);
pci_config_writeb(d, 0xd2, 0x09); /* enable SMBus io space */
- pm_sci_int = pci_config_readb(d, PCI_INTERRUPT_LINE);
-#ifdef BX_USE_SMM
+#if (CONFIG_USE_SMM == 1)
smm_init(d);
#endif
- acpi_enabled = 1;
}
}
-void pci_for_each_device(void (*init_func)(PCIDevice *d))
+void pci_for_each_device(void (*init_func)(PCIDevice d))
{
- PCIDevice d1, *d = &d1;
int bus, devfn;
u16 vendor_id, device_id;
for(bus = 0; bus < 1; bus++) {
for(devfn = 0; devfn < 256; devfn++) {
- d->bus = bus;
- d->devfn = devfn;
+ PCIDevice d = pci_bd(bus, devfn);
vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
device_id = pci_config_readw(d, PCI_DEVICE_ID);
if (vendor_id != 0xffff || device_id != 0xffff) {
{
pci_bios_io_addr = 0xc000;
pci_bios_mem_addr = 0xf0000000;
- pci_bios_bigmem_addr = ram_size;
+ pci_bios_bigmem_addr = GET_EBDA(ram_size);
if (pci_bios_bigmem_addr < 0x90000000)
pci_bios_bigmem_addr = 0x90000000;
*pp = q;
}
-static unsigned long align(unsigned long addr, unsigned long v)
-{
- return (addr + v - 1) & ~(v - 1);
-}
-
static void mptable_init(void)
{
u8 *mp_config_table, *q, *float_pointer_struct;
int ioapic_id, i, len;
int mp_config_table_size;
-#ifdef BX_QEMU
+#if (CONFIG_QEMU == 1)
if (smp_cpus <= 1)
return;
#endif
-#ifdef BX_USE_EBDA_TABLES
- mp_config_table = (u8 *)(ram_size - ACPI_DATA_SIZE - MPTABLE_MAX_SIZE);
+#if (CONFIG_USE_EBDA_TABLES == 1)
+ mp_config_table = (u8 *)(GET_EBDA(ram_size) - CONFIG_ACPI_DATA_SIZE
+ - MPTABLE_MAX_SIZE);
#else
- bios_table_cur_addr = align(bios_table_cur_addr, 16);
+ bios_table_cur_addr = ALIGN(bios_table_cur_addr, 16);
mp_config_table = (u8 *)bios_table_cur_addr;
#endif
q = mp_config_table;
putle16(&q, 0); /* table length (patched later) */
putb(&q, 4); /* spec rev */
putb(&q, 0); /* checksum (patched later) */
-#ifdef BX_QEMU
+#if (CONFIG_QEMU == 1)
putstr(&q, "QEMUCPU "); /* OEM id */
#else
putstr(&q, "BOCHSCPU");
mp_config_table_size = q - mp_config_table;
-#ifndef BX_USE_EBDA_TABLES
+#if (CONFIG_USE_EBDA_TABLES != 1)
bios_table_cur_addr += mp_config_table_size;
#endif
/* floating pointer structure */
-#ifdef BX_USE_EBDA_TABLES
- ebda_cur_addr = align(ebda_cur_addr, 16);
+#if (CONFIG_USE_EBDA_TABLES == 1)
+ ebda_cur_addr = ALIGN(ebda_cur_addr, 16);
float_pointer_struct = (u8 *)ebda_cur_addr;
#else
- bios_table_cur_addr = align(bios_table_cur_addr, 16);
+ bios_table_cur_addr = ALIGN(bios_table_cur_addr, 16);
float_pointer_struct = (u8 *)bios_table_cur_addr;
#endif
q = float_pointer_struct;
putb(&q, 0);
float_pointer_struct[10] = -checksum(float_pointer_struct
, q - float_pointer_struct);
-#ifdef BX_USE_EBDA_TABLES
+#if (CONFIG_USE_EBDA_TABLES == 1)
ebda_cur_addr += (q - float_pointer_struct);
#else
bios_table_cur_addr += (q - float_pointer_struct);
#endif
- BX_INFO("MP table addr=0x%08lx MPC table addr=0x%08lx size=0x%x\n",
+ dprintf(1, "MP table addr=0x%08lx MPC table addr=0x%08lx size=0x%x\n",
(unsigned long)float_pointer_struct,
(unsigned long)mp_config_table,
mp_config_table_size);
}
-/****************************************************/
-/* ACPI tables init */
-
-/* Table structure from Linux kernel (the ACPI tables are under the
- BSD license) */
-
-#define ACPI_TABLE_HEADER_DEF /* ACPI common table header */ \
- u8 signature [4]; /* ACPI signature (4 ASCII characters) */\
- u32 length; /* Length of table, in bytes, including header */\
- u8 revision; /* ACPI Specification minor version # */\
- u8 checksum; /* To make sum of entire table == 0 */\
- u8 oem_id [6]; /* OEM identification */\
- u8 oem_table_id [8]; /* OEM table identification */\
- u32 oem_revision; /* OEM revision number */\
- u8 asl_compiler_id [4]; /* ASL compiler vendor ID */\
- u32 asl_compiler_revision; /* ASL compiler revision number */
-
-
-struct acpi_table_header /* ACPI common table header */
-{
- ACPI_TABLE_HEADER_DEF
-};
-
-struct rsdp_descriptor /* Root System Descriptor Pointer */
-{
- u8 signature [8]; /* ACPI signature, contains "RSD PTR " */
- u8 checksum; /* To make sum of struct == 0 */
- u8 oem_id [6]; /* OEM identification */
- u8 revision; /* Must be 0 for 1.0, 2 for 2.0 */
- u32 rsdt_physical_address; /* 32-bit physical address of RSDT */
- u32 length; /* XSDT Length in bytes including hdr */
- u64 xsdt_physical_address; /* 64-bit physical address of XSDT */
- u8 extended_checksum; /* Checksum of entire table */
- u8 reserved [3]; /* Reserved field must be 0 */
-};
-
-/*
- * ACPI 1.0 Root System Description Table (RSDT)
- */
-struct rsdt_descriptor_rev1
-{
- ACPI_TABLE_HEADER_DEF /* ACPI common table header */
- u32 table_offset_entry [3]; /* Array of pointers to other */
- /* ACPI tables */
-};
-
-/*
- * ACPI 1.0 Firmware ACPI Control Structure (FACS)
- */
-struct facs_descriptor_rev1
-{
- u8 signature[4]; /* ACPI Signature */
- u32 length; /* Length of structure, in bytes */
- u32 hardware_signature; /* Hardware configuration signature */
- u32 firmware_waking_vector; /* ACPI OS waking vector */
- u32 global_lock; /* Global Lock */
- u32 S4bios_f : 1; /* Indicates if S4BIOS support is present */
- u32 reserved1 : 31; /* Must be 0 */
- u8 resverved3 [40]; /* Reserved - must be zero */
-};
-
-
-/*
- * ACPI 1.0 Fixed ACPI Description Table (FADT)
- */
-struct fadt_descriptor_rev1
-{
- ACPI_TABLE_HEADER_DEF /* ACPI common table header */
- u32 firmware_ctrl; /* Physical address of FACS */
- u32 dsdt; /* Physical address of DSDT */
- u8 model; /* System Interrupt Model */
- u8 reserved1; /* Reserved */
- u16 sci_int; /* System vector of SCI interrupt */
- u32 smi_cmd; /* Port address of SMI command port */
- u8 acpi_enable; /* Value to write to smi_cmd to enable ACPI */
- u8 acpi_disable; /* Value to write to smi_cmd to disable ACPI */
- u8 S4bios_req; /* Value to write to SMI CMD to enter S4BIOS state */
- u8 reserved2; /* Reserved - must be zero */
- u32 pm1a_evt_blk; /* Port address of Power Mgt 1a acpi_event Reg Blk */
- u32 pm1b_evt_blk; /* Port address of Power Mgt 1b acpi_event Reg Blk */
- u32 pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */
- u32 pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */
- u32 pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */
- u32 pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */
- u32 gpe0_blk; /* Port addr of General Purpose acpi_event 0 Reg Blk */
- u32 gpe1_blk; /* Port addr of General Purpose acpi_event 1 Reg Blk */
- u8 pm1_evt_len; /* Byte length of ports at pm1_x_evt_blk */
- u8 pm1_cnt_len; /* Byte length of ports at pm1_x_cnt_blk */
- u8 pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */
- u8 pm_tmr_len; /* Byte Length of ports at pm_tm_blk */
- u8 gpe0_blk_len; /* Byte Length of ports at gpe0_blk */
- u8 gpe1_blk_len; /* Byte Length of ports at gpe1_blk */
- u8 gpe1_base; /* Offset in gpe model where gpe1 events start */
- u8 reserved3; /* Reserved */
- u16 plvl2_lat; /* Worst case HW latency to enter/exit C2 state */
- u16 plvl3_lat; /* Worst case HW latency to enter/exit C3 state */
- u16 flush_size; /* Size of area read to flush caches */
- u16 flush_stride; /* Stride used in flushing caches */
- u8 duty_offset; /* Bit location of duty cycle field in p_cnt reg */
- u8 duty_width; /* Bit width of duty cycle field in p_cnt reg */
- u8 day_alrm; /* Index to day-of-month alarm in RTC CMOS RAM */
- u8 mon_alrm; /* Index to month-of-year alarm in RTC CMOS RAM */
- u8 century; /* Index to century in RTC CMOS RAM */
- u8 reserved4; /* Reserved */
- u8 reserved4a; /* Reserved */
- u8 reserved4b; /* Reserved */
-#if 0
- u32 wb_invd : 1; /* The wbinvd instruction works properly */
- u32 wb_invd_flush : 1; /* The wbinvd flushes but does not invalidate */
- u32 proc_c1 : 1; /* All processors support C1 state */
- u32 plvl2_up : 1; /* C2 state works on MP system */
- u32 pwr_button : 1; /* Power button is handled as a generic feature */
- u32 sleep_button : 1; /* Sleep button is handled as a generic feature, or not present */
- u32 fixed_rTC : 1; /* RTC wakeup stat not in fixed register space */
- u32 rtcs4 : 1; /* RTC wakeup stat not possible from S4 */
- u32 tmr_val_ext : 1; /* The tmr_val width is 32 bits (0 = 24 bits) */
- u32 reserved5 : 23; /* Reserved - must be zero */
-#else
- u32 flags;
-#endif
-};
-
-/*
- * MADT values and structures
- */
-
-/* Values for MADT PCATCompat */
-
-#define DUAL_PIC 0
-#define MULTIPLE_APIC 1
-
-
-/* Master MADT */
-
-struct multiple_apic_table
-{
- ACPI_TABLE_HEADER_DEF /* ACPI common table header */
- u32 local_apic_address; /* Physical address of local APIC */
-#if 0
- u32 PCATcompat : 1; /* A one indicates system also has dual 8259s */
- u32 reserved1 : 31;
-#else
- u32 flags;
-#endif
-};
-
-
-/* Values for Type in APIC_HEADER_DEF */
-
-#define APIC_PROCESSOR 0
-#define APIC_IO 1
-#define APIC_XRUPT_OVERRIDE 2
-#define APIC_NMI 3
-#define APIC_LOCAL_NMI 4
-#define APIC_ADDRESS_OVERRIDE 5
-#define APIC_IO_SAPIC 6
-#define APIC_LOCAL_SAPIC 7
-#define APIC_XRUPT_SOURCE 8
-#define APIC_RESERVED 9 /* 9 and greater are reserved */
-
-/*
- * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
- */
-#define APIC_HEADER_DEF /* Common APIC sub-structure header */\
- u8 type; \
- u8 length;
-
-/* Sub-structures for MADT */
-
-struct madt_processor_apic
-{
- APIC_HEADER_DEF
- u8 processor_id; /* ACPI processor id */
- u8 local_apic_id; /* Processor's local APIC id */
-#if 0
- u32 processor_enabled: 1; /* Processor is usable if set */
- u32 reserved2 : 31; /* Reserved, must be zero */
-#else
- u32 flags;
-#endif
-};
-
-struct madt_io_apic
-{
- APIC_HEADER_DEF
- u8 io_apic_id; /* I/O APIC ID */
- u8 reserved; /* Reserved - must be zero */
- u32 address; /* APIC physical address */
- u32 interrupt; /* Global system interrupt where INTI
- * lines start */
-};
-
-#include "acpi-dsdt.hex"
-
-static inline u16 cpu_to_le16(u16 x)
-{
- return x;
-}
-
-static inline u32 cpu_to_le32(u32 x)
-{
- return x;
-}
-
-static void acpi_build_table_header(struct acpi_table_header *h,
- char *sig, int len, u8 rev)
-{
- memcpy(h->signature, sig, 4);
- h->length = cpu_to_le32(len);
- h->revision = rev;
-#ifdef BX_QEMU
- memcpy(h->oem_id, "QEMU ", 6);
- memcpy(h->oem_table_id, "QEMU", 4);
-#else
- memcpy(h->oem_id, "BOCHS ", 6);
- memcpy(h->oem_table_id, "BXPC", 4);
-#endif
- memcpy(h->oem_table_id + 4, sig, 4);
- h->oem_revision = cpu_to_le32(1);
-#ifdef BX_QEMU
- memcpy(h->asl_compiler_id, "QEMU", 4);
-#else
- memcpy(h->asl_compiler_id, "BXPC", 4);
-#endif
- h->asl_compiler_revision = cpu_to_le32(1);
- h->checksum = -checksum((void *)h, len);
-}
-
-int acpi_build_processor_ssdt(u8 *ssdt)
-{
- u8 *ssdt_ptr = ssdt;
- int i, length;
- int acpi_cpus = smp_cpus > 0xff ? 0xff : smp_cpus;
-
- ssdt_ptr[9] = 0; // checksum;
- ssdt_ptr += sizeof(struct acpi_table_header);
-
- // caluculate the length of processor block and scope block excluding PkgLength
- length = 0x0d * acpi_cpus + 4;
-
- // build processor scope header
- *(ssdt_ptr++) = 0x10; // ScopeOp
- if (length <= 0x3e) {
- *(ssdt_ptr++) = length + 1;
- } else {
- *(ssdt_ptr++) = 0x7F;
- *(ssdt_ptr++) = (length + 2) >> 6;
- }
- *(ssdt_ptr++) = '_'; // Name
- *(ssdt_ptr++) = 'P';
- *(ssdt_ptr++) = 'R';
- *(ssdt_ptr++) = '_';
-
- // build object for each processor
- for(i=0;i<acpi_cpus;i++) {
- *(ssdt_ptr++) = 0x5B; // ProcessorOp
- *(ssdt_ptr++) = 0x83;
- *(ssdt_ptr++) = 0x0B; // Length
- *(ssdt_ptr++) = 'C'; // Name (CPUxx)
- *(ssdt_ptr++) = 'P';
- if ((i & 0xf0) != 0)
- *(ssdt_ptr++) = (i >> 4) < 0xa ? (i >> 4) + '0' : (i >> 4) + 'A' - 0xa;
- else
- *(ssdt_ptr++) = 'U';
- *(ssdt_ptr++) = (i & 0xf) < 0xa ? (i & 0xf) + '0' : (i & 0xf) + 'A' - 0xa;
- *(ssdt_ptr++) = i;
- *(ssdt_ptr++) = 0x10; // Processor block address
- *(ssdt_ptr++) = 0xb0;
- *(ssdt_ptr++) = 0;
- *(ssdt_ptr++) = 0;
- *(ssdt_ptr++) = 6; // Processor block length
- }
-
- acpi_build_table_header((struct acpi_table_header *)ssdt,
- "SSDT", ssdt_ptr - ssdt, 1);
-
- return ssdt_ptr - ssdt;
-}
-
-/* base_addr must be a multiple of 4KB */
-void acpi_bios_init(void)
-{
- struct rsdp_descriptor *rsdp;
- struct rsdt_descriptor_rev1 *rsdt;
- struct fadt_descriptor_rev1 *fadt;
- struct facs_descriptor_rev1 *facs;
- struct multiple_apic_table *madt;
- u8 *dsdt, *ssdt;
- u32 base_addr, rsdt_addr, fadt_addr, addr, facs_addr, dsdt_addr, ssdt_addr;
- u32 acpi_tables_size, madt_addr, madt_size;
- int i;
-
- /* reserve memory space for tables */
-#ifdef BX_USE_EBDA_TABLES
- ebda_cur_addr = align(ebda_cur_addr, 16);
- rsdp = (void *)(ebda_cur_addr);
- ebda_cur_addr += sizeof(*rsdp);
-#else
- bios_table_cur_addr = align(bios_table_cur_addr, 16);
- rsdp = (void *)(bios_table_cur_addr);
- bios_table_cur_addr += sizeof(*rsdp);
-#endif
-
- addr = base_addr = ram_size - ACPI_DATA_SIZE;
- rsdt_addr = addr;
- rsdt = (void *)(addr);
- addr += sizeof(*rsdt);
-
- fadt_addr = addr;
- fadt = (void *)(addr);
- addr += sizeof(*fadt);
-
- /* XXX: FACS should be in RAM */
- addr = (addr + 63) & ~63; /* 64 byte alignment for FACS */
- facs_addr = addr;
- facs = (void *)(addr);
- addr += sizeof(*facs);
-
- dsdt_addr = addr;
- dsdt = (void *)(addr);
- addr += sizeof(AmlCode);
-
- ssdt_addr = addr;
- ssdt = (void *)(addr);
- addr += acpi_build_processor_ssdt(ssdt);
-
- addr = (addr + 7) & ~7;
- madt_addr = addr;
- madt_size = sizeof(*madt) +
- sizeof(struct madt_processor_apic) * smp_cpus +
- sizeof(struct madt_io_apic);
- madt = (void *)(addr);
- addr += madt_size;
-
- acpi_tables_size = addr - base_addr;
-
- BX_INFO("ACPI tables: RSDP addr=0x%08lx ACPI DATA addr=0x%08lx size=0x%x\n",
- (unsigned long)rsdp,
- (unsigned long)rsdt, acpi_tables_size);
-
- /* RSDP */
- memset(rsdp, 0, sizeof(*rsdp));
- memcpy(rsdp->signature, "RSD PTR ", 8);
-#ifdef BX_QEMU
- memcpy(rsdp->oem_id, "QEMU ", 6);
-#else
- memcpy(rsdp->oem_id, "BOCHS ", 6);
-#endif
- rsdp->rsdt_physical_address = cpu_to_le32(rsdt_addr);
- rsdp->checksum = -checksum((void *)rsdp, 20);
-
- /* RSDT */
- memset(rsdt, 0, sizeof(*rsdt));
- rsdt->table_offset_entry[0] = cpu_to_le32(fadt_addr);
- rsdt->table_offset_entry[1] = cpu_to_le32(madt_addr);
- rsdt->table_offset_entry[2] = cpu_to_le32(ssdt_addr);
- acpi_build_table_header((struct acpi_table_header *)rsdt,
- "RSDT", sizeof(*rsdt), 1);
-
- /* FADT */
- memset(fadt, 0, sizeof(*fadt));
- fadt->firmware_ctrl = cpu_to_le32(facs_addr);
- fadt->dsdt = cpu_to_le32(dsdt_addr);
- fadt->model = 1;
- fadt->reserved1 = 0;
- fadt->sci_int = cpu_to_le16(pm_sci_int);
- fadt->smi_cmd = cpu_to_le32(SMI_CMD_IO_ADDR);
- fadt->acpi_enable = 0xf1;
- fadt->acpi_disable = 0xf0;
- fadt->pm1a_evt_blk = cpu_to_le32(pm_io_base);
- fadt->pm1a_cnt_blk = cpu_to_le32(pm_io_base + 0x04);
- fadt->pm_tmr_blk = cpu_to_le32(pm_io_base + 0x08);
- fadt->pm1_evt_len = 4;
- fadt->pm1_cnt_len = 2;
- fadt->pm_tmr_len = 4;
- fadt->plvl2_lat = cpu_to_le16(50);
- fadt->plvl3_lat = cpu_to_le16(50);
- fadt->plvl3_lat = cpu_to_le16(50);
- /* WBINVD + PROC_C1 + PWR_BUTTON + SLP_BUTTON + FIX_RTC */
- fadt->flags = cpu_to_le32((1 << 0) | (1 << 2) | (1 << 4) | (1 << 5) | (1 << 6));
- acpi_build_table_header((struct acpi_table_header *)fadt, "FACP",
- sizeof(*fadt), 1);
-
- /* FACS */
- memset(facs, 0, sizeof(*facs));
- memcpy(facs->signature, "FACS", 4);
- facs->length = cpu_to_le32(sizeof(*facs));
-
- /* DSDT */
- memcpy(dsdt, AmlCode, sizeof(AmlCode));
-
- /* MADT */
- {
- struct madt_processor_apic *apic;
- struct madt_io_apic *io_apic;
-
- memset(madt, 0, madt_size);
- madt->local_apic_address = cpu_to_le32(0xfee00000);
- madt->flags = cpu_to_le32(1);
- apic = (void *)(madt + 1);
- for(i=0;i<smp_cpus;i++) {
- apic->type = APIC_PROCESSOR;
- apic->length = sizeof(*apic);
- apic->processor_id = i;
- apic->local_apic_id = i;
- apic->flags = cpu_to_le32(1);
- apic++;
- }
- io_apic = (void *)apic;
- io_apic->type = APIC_IO;
- io_apic->length = sizeof(*io_apic);
- io_apic->io_apic_id = smp_cpus;
- io_apic->address = cpu_to_le32(0xfec00000);
- io_apic->interrupt = cpu_to_le32(0);
-
- acpi_build_table_header((struct acpi_table_header *)madt,
- "APIC", madt_size, 1);
- }
-}
-
/* SMBIOS entry point -- must be written to a 16-bit aligned address
between 0xf0000 and 0xfffff.
*/
p->embedded_controller_minor_release = 0xff;
start += sizeof(struct smbios_type_0);
- memcpy((char *)start, BX_APPNAME, sizeof(BX_APPNAME));
- start += sizeof(BX_APPNAME);
+ memcpy((char *)start, CONFIG_APPNAME, sizeof(CONFIG_APPNAME));
+ start += sizeof(CONFIG_APPNAME);
memcpy((char *)start, RELEASE_DATE_STR, sizeof(RELEASE_DATE_STR));
start += sizeof(RELEASE_DATE_STR);
*((u8 *)start) = 0;
{
unsigned cpu_num, nr_structs = 0, max_struct_size = 0;
char *start, *p, *q;
- int memsize = ram_size / (1024 * 1024);
+ int memsize = GET_EBDA(ram_size) / (1024 * 1024);
-#ifdef BX_USE_EBDA_TABLES
- ebda_cur_addr = align(ebda_cur_addr, 16);
+#if (CONFIG_USE_EBDA_TABLES == 1)
+ ebda_cur_addr = ALIGN(ebda_cur_addr, 16);
start = (void *)(ebda_cur_addr);
#else
- bios_table_cur_addr = align(bios_table_cur_addr, 16);
+ bios_table_cur_addr = ALIGN(bios_table_cur_addr, 16);
start = (void *)(bios_table_cur_addr);
#endif
- p = (char *)start + sizeof(struct smbios_entry_point);
+ p = (char *)start + sizeof(struct smbios_entry_point);
#define add_struct(fn) { \
q = (fn); \
(u32)(start + sizeof(struct smbios_entry_point)),
nr_structs);
-#ifdef BX_USE_EBDA_TABLES
+#if (CONFIG_USE_EBDA_TABLES == 1)
ebda_cur_addr += (p - (char *)start);
#else
bios_table_cur_addr += (p - (char *)start);
#endif
- BX_INFO("SMBIOS table addr=0x%08lx\n", (unsigned long)start);
+ dprintf(1, "SMBIOS table addr=0x%08lx\n", (unsigned long)start);
}
void rombios32_init(void)
{
- BX_INFO("Starting rombios32\n");
+ if (CONFIG_COREBOOT)
+ // XXX - not supported on coreboot yet.
+ return;
+
+ dprintf(1, "Starting rombios32\n");
- ram_probe();
+#if (CONFIG_USE_EBDA_TABLES == 1)
+ ebda_cur_addr = ((*(u16 *)(0x40e)) << 4) + 0x380;
+ dprintf(1, "ebda_cur_addr: 0x%08lx\n", ebda_cur_addr);
+#endif
cpu_probe();
smp_probe();
- uuid_probe();
-
pci_bios_init();
if (bios_table_cur_addr != 0) {
mptable_init();
- smbios_init();
+ uuid_probe();
- if (acpi_enabled)
- acpi_bios_init();
+ smbios_init();
- bios_lock_shadow_ram();
+ acpi_bios_init();
- BX_INFO("bios_table_cur_addr: 0x%08lx\n", bios_table_cur_addr);
+ dprintf(1, "bios_table_cur_addr: 0x%08x\n", bios_table_cur_addr);
if (bios_table_cur_addr > bios_table_end_addr)
BX_PANIC("bios_table_end_addr overflow!\n");
}
projects / seabios.git / blobdiff