// License along with this library; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-#include "util.h" // BX_INFO
+#include "util.h" // dprintf
#include "pci.h" // PCIDevice
#include "types.h" // u32
#include "config.h" // CONFIG_*
smp_cpus = readw((void *)CPU_COUNT_ADDR);
}
- BX_INFO("Found %d cpu(s)\n", smp_cpus);
+ dprintf(1, "Found %d cpu(s)\n", smp_cpus);
}
/****************************************************/
static u8 pci_irqs[4] = { 11, 9, 11, 9 };
static PCIDevice i440_pcidev;
-static void pci_set_io_region_addr(PCIDevice *d, int region_num, u32 addr)
+static void pci_set_io_region_addr(PCIDevice d, int region_num, u32 addr)
{
u16 cmd;
u32 ofs, old_addr;
old_addr = pci_config_readl(d, ofs);
pci_config_writel(d, ofs, addr);
- BX_INFO("region %d: 0x%08x\n", region_num, addr);
+ dprintf(1, "region %d: 0x%08x\n", region_num, addr);
/* enable memory mappings */
cmd = pci_config_readw(d, PCI_COMMAND);
/* return the global irq number corresponding to a given device irq
pin. We could also use the bus number to have a more precise
mapping. */
-static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
+static int pci_slot_get_pirq(PCIDevice pci_dev, int irq_num)
{
int slot_addend;
- slot_addend = (pci_dev->devfn >> 3) - 1;
+ slot_addend = (pci_dev.devfn >> 3) - 1;
return (irq_num + slot_addend) & 3;
}
static void
-copy_bios(PCIDevice *d, int v)
+copy_bios(PCIDevice d, int v)
{
pci_config_writeb(d, 0x59, v);
memcpy((void *)0x000f0000, (void *)BIOS_TMP_STORAGE, 0x10000);
(__addr - __start < __size); \
})
-static void bios_shadow_init(PCIDevice *d)
+static void bios_shadow_init(PCIDevice d)
{
bios_table_cur_addr = 0xf0000 | OFFSET_freespace2_start;
bios_table_end_addr = 0xf0000 | OFFSET_freespace2_end;
- BX_INFO("bios_table_addr: 0x%08lx end=0x%08lx\n",
+ dprintf(1, "bios_table_addr: 0x%08lx end=0x%08lx\n",
bios_table_cur_addr, bios_table_end_addr);
/* remap the BIOS to shadow RAM an keep it read/write while we
// Current code is in shadowed area. Perform the copy from
// the code that is in the temporary location.
u32 pos = (u32)copy_bios - 0xf0000 + BIOS_TMP_STORAGE;
- void (*func)(PCIDevice *, int) = (void*)pos;
+ void (*func)(PCIDevice, int) = (void*)pos;
func(d, v);
} else {
copy_bios(d, v);
// Clear the area just copied.
memset((void *)BIOS_TMP_STORAGE, 0, 0x10000);
- i440_pcidev = *d;
+ i440_pcidev = d;
}
static void bios_lock_shadow_ram(void)
{
- PCIDevice *d = &i440_pcidev;
+ PCIDevice d = i440_pcidev;
int v;
wbinvd();
pci_config_writeb(d, 0x59, v);
}
-static void pci_bios_init_bridges(PCIDevice *d)
+static void pci_bios_init_bridges(PCIDevice d)
{
u16 vendor_id, device_id;
}
outb(elcr[0], 0x4d0);
outb(elcr[1], 0x4d1);
- BX_INFO("PIIX3 init: elcr=%02x %02x\n",
+ dprintf(1, "PIIX3 init: elcr=%02x %02x\n",
elcr[0], elcr[1]);
} else if (vendor_id == 0x8086 && device_id == 0x1237) {
/* i440 PCI bridge */
extern u8 smm_code_start, smm_code_end;
#if (CONFIG_USE_SMM == 1)
-static void smm_init(PCIDevice *d)
+static void smm_init(PCIDevice d)
{
u32 value;
;
/* enable the SMM memory window */
- pci_config_writeb(&i440_pcidev, 0x72, 0x02 | 0x48);
+ pci_config_writeb(i440_pcidev, 0x72, 0x02 | 0x48);
/* copy the SMM code */
memcpy((void *)0xa8000, &smm_code_start,
wbinvd();
/* close the SMM memory window and enable normal SMM */
- pci_config_writeb(&i440_pcidev, 0x72, 0x02 | 0x08);
+ pci_config_writeb(i440_pcidev, 0x72, 0x02 | 0x08);
}
}
#endif
-static void pci_bios_init_device(PCIDevice *d)
+static void pci_bios_init_device(PCIDevice d)
{
int class;
u32 *paddr;
class = pci_config_readw(d, PCI_CLASS_DEVICE);
vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
device_id = pci_config_readw(d, PCI_DEVICE_ID);
- BX_INFO("PCI: bus=%d devfn=0x%02x: vendor_id=0x%04x device_id=0x%04x\n",
- d->bus, d->devfn, vendor_id, device_id);
+ dprintf(1, "PCI: bus=%d devfn=0x%02x: vendor_id=0x%04x device_id=0x%04x\n",
+ d.bus, d.devfn, vendor_id, device_id);
switch(class) {
case 0x0101:
if (vendor_id == 0x8086 && device_id == 0x7010) {
}
}
-void pci_for_each_device(void (*init_func)(PCIDevice *d))
+void pci_for_each_device(void (*init_func)(PCIDevice d))
{
- PCIDevice d1, *d = &d1;
int bus, devfn;
u16 vendor_id, device_id;
for(bus = 0; bus < 1; bus++) {
for(devfn = 0; devfn < 256; devfn++) {
- d->bus = bus;
- d->devfn = devfn;
+ PCIDevice d = pci_bd(bus, devfn);
vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
device_id = pci_config_readw(d, PCI_DEVICE_ID);
if (vendor_id != 0xffff || device_id != 0xffff) {
#else
bios_table_cur_addr += (q - float_pointer_struct);
#endif
- BX_INFO("MP table addr=0x%08lx MPC table addr=0x%08lx size=0x%x\n",
+ dprintf(1, "MP table addr=0x%08lx MPC table addr=0x%08lx size=0x%x\n",
(unsigned long)float_pointer_struct,
(unsigned long)mp_config_table,
mp_config_table_size);
acpi_tables_size = addr - base_addr;
- BX_INFO("ACPI tables: RSDP addr=0x%08lx ACPI DATA addr=0x%08lx size=0x%x\n",
+ dprintf(1, "ACPI tables: RSDP addr=0x%08lx"
+ " ACPI DATA addr=0x%08lx size=0x%x\n",
(unsigned long)rsdp,
(unsigned long)rsdt, acpi_tables_size);
bios_table_cur_addr += (p - (char *)start);
#endif
- BX_INFO("SMBIOS table addr=0x%08lx\n", (unsigned long)start);
+ dprintf(1, "SMBIOS table addr=0x%08lx\n", (unsigned long)start);
}
void rombios32_init(void)
// XXX - not supported on coreboot yet.
return;
- BX_INFO("Starting rombios32\n");
+ dprintf(1, "Starting rombios32\n");
#if (CONFIG_USE_EBDA_TABLES == 1)
ebda_cur_addr = ((*(u16 *)(0x40e)) << 4) + 0x380;
- BX_INFO("ebda_cur_addr: 0x%08lx\n", ebda_cur_addr);
+ dprintf(1, "ebda_cur_addr: 0x%08lx\n", ebda_cur_addr);
#endif
cpu_probe();
bios_lock_shadow_ram();
- BX_INFO("bios_table_cur_addr: 0x%08lx\n", bios_table_cur_addr);
+ dprintf(1, "bios_table_cur_addr: 0x%08lx\n", bios_table_cur_addr);
if (bios_table_cur_addr > bios_table_end_addr)
BX_PANIC("bios_table_end_addr overflow!\n");
}
projects / seabios.git / blobdiff