Add support for 32bit PCI BIOS entry.

[seabios.git] / src / pmm.c

diff --git a/src/pmm.c b/src/pmm.c
index a72167bb50c518930438c8834317095e0eb5ee01..dab8fb36b13c48cf09813720e2680bd5af48b077 100644 (file)
--- a/src/pmm.c
+++ b/src/pmm.c
@@ -14,8 +14,13 @@
 #if MODESEGMENT
 // The 16bit pmm entry points runs in "big real" mode, and can
 // therefore read/write to the 32bit malloc variables.
-#define GET_PMMVAR(var) GET_FARVAR(0, (var))
-#define SET_PMMVAR(var, val) SET_FARVAR(0, (var), (val))
+#define GET_PMMVAR(var) ({                      \
+            SET_SEG(ES, 0);                     \
+            __GET_VAR("addr32 ", ES, (var)); })
+#define SET_PMMVAR(var, val) do {               \
+        SET_SEG(ES, 0);                         \
+        __SET_VAR("addr32 ", ES, (var), (val)); \
+    } while (0)
 #else
 #define GET_PMMVAR(var) (var)
 #define SET_PMMVAR(var, val) do { (var) = (val); } while (0)
@@ -285,10 +290,11 @@ malloc_setup()
     PMMAllocs = NULL;
 
     // Memory in 0xf0000 area.
-    extern u8 code32_start[];
-    if ((u32)code32_start > BUILD_BIOS_ADDR)
+    extern u8 code32flat_start[];
+    if ((u32)code32flat_start > BUILD_BIOS_ADDR)
         // Clear unused parts of f-segment
-        memset((void*)BUILD_BIOS_ADDR, 0, (u32)code32_start - BUILD_BIOS_ADDR);
+        memset((void*)BUILD_BIOS_ADDR, 0
+               , (u32)code32flat_start - BUILD_BIOS_ADDR);
     memset(BiosTableSpace, 0, CONFIG_MAX_BIOSTABLE);
     ZoneFSeg.bottom = (u32)BiosTableSpace;
     ZoneFSeg.top = ZoneFSeg.cur = ZoneFSeg.bottom + CONFIG_MAX_BIOSTABLE;