Change license from GPLv3 to LGPLv3.

[seabios.git] / src / pciinit.c

diff --git a/src/pciinit.c b/src/pciinit.c
index 28bee74ff6ddef5aff77acaded9d528278f8173e..78f421225531106ec720c8a89551a0f0d9c597a0 100644 (file)
--- a/src/pciinit.c
+++ b/src/pciinit.c
@@ -3,7 +3,7 @@
 // Copyright (C) 2008  Kevin O'Connor <kevin@koconnor.net>
 // Copyright (C) 2006 Fabrice Bellard
 //
-// This file may be distributed under the terms of the GNU GPLv3 license.
+// This file may be distributed under the terms of the GNU LGPLv3 license.
 
 #include "util.h" // dprintf
 #include "pci.h" // pci_config_readl
@@ -11,10 +11,6 @@
 #include "pci_ids.h" // PCI_VENDOR_ID_INTEL
 #include "pci_regs.h" // PCI_COMMAND
 
-#define PCI_ADDRESS_SPACE_MEM          0x00
-#define PCI_ADDRESS_SPACE_IO           0x01
-#define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08
-
 #define PCI_ROM_SLOT 6
 #define PCI_NUM_REGIONS 7
 
@@ -22,17 +18,23 @@ static u32 pci_bios_io_addr;
 static u32 pci_bios_mem_addr;
 static u32 pci_bios_bigmem_addr;
 /* host irqs corresponding to PCI irqs A-D */
-static u8 pci_irqs[4] = { 11, 9, 11, 9 };
+static u8 pci_irqs[4] = {
+#if CONFIG_KVM
+    10, 10, 11, 11
+#else
+    11, 9, 11, 9
+#endif
+};
 
 static void pci_set_io_region_addr(u16 bdf, int region_num, u32 addr)
 {
     u16 cmd;
     u32 ofs, old_addr;
 
-    if ( region_num == PCI_ROM_SLOT ) {
-        ofs = 0x30;
-    }else{
-        ofs = 0x10 + region_num * 4;
+    if (region_num == PCI_ROM_SLOT) {
+        ofs = PCI_ROM_ADDRESS;
+    } else {
+        ofs = PCI_BASE_ADDRESS_0 + region_num * 4;
     }
 
     old_addr = pci_config_readl(bdf, ofs);
@@ -42,12 +44,12 @@ static void pci_set_io_region_addr(u16 bdf, int region_num, u32 addr)
 
     /* enable memory mappings */
     cmd = pci_config_readw(bdf, PCI_COMMAND);
-    if ( region_num == PCI_ROM_SLOT )
-        cmd |= 2;
-    else if (old_addr & PCI_ADDRESS_SPACE_IO)
-        cmd |= 1;
+    if (region_num == PCI_ROM_SLOT)
+        cmd |= PCI_COMMAND_MEMORY;
+    else if (old_addr & PCI_BASE_ADDRESS_SPACE_IO)
+        cmd |= PCI_COMMAND_IO;
     else
-        cmd |= 2;
+        cmd |= PCI_COMMAND_MEMORY;
     pci_config_writew(bdf, PCI_COMMAND, cmd);
 }
 
@@ -101,7 +103,7 @@ static void pci_bios_init_device(u16 bdf)
     dprintf(1, "PCI: bus=%d devfn=0x%02x: vendor_id=0x%04x device_id=0x%04x\n"
             , pci_bdf_to_bus(bdf), pci_bdf_to_devfn(bdf), vendor_id, device_id);
     switch(class) {
-    case 0x0101:
+    case PCI_CLASS_STORAGE_IDE:
         if (vendor_id == PCI_VENDOR_ID_INTEL
             && (device_id == PCI_DEVICE_ID_INTEL_82371SB_1
                 || device_id == PCI_DEVICE_ID_INTEL_82371AB)) {
@@ -117,13 +119,13 @@ static void pci_bios_init_device(u16 bdf)
             pci_set_io_region_addr(bdf, 3, 0x374);
         }
         break;
-    case 0x0300:
+    case PCI_CLASS_DISPLAY_VGA:
         if (vendor_id != 0x1234)
             goto default_map;
         /* VGA: map frame buffer to default Bochs VBE address */
         pci_set_io_region_addr(bdf, 0, 0xE0000000);
         break;
-    case 0x0800:
+    case PCI_CLASS_SYSTEM_PIC:
         /* PIC */
         if (vendor_id == PCI_VENDOR_ID_IBM) {
             /* IBM */
@@ -143,19 +145,19 @@ static void pci_bios_init_device(u16 bdf)
     default:
     default_map:
         /* default memory mappings */
-        for(i = 0; i < PCI_NUM_REGIONS; i++) {
+        for (i = 0; i < PCI_NUM_REGIONS; i++) {
             int ofs;
             u32 val, size;
 
             if (i == PCI_ROM_SLOT)
-                ofs = 0x30;
+                ofs = PCI_ROM_ADDRESS;
             else
-                ofs = 0x10 + i * 4;
+                ofs = PCI_BASE_ADDRESS_0 + i * 4;
             pci_config_writel(bdf, ofs, 0xffffffff);
             val = pci_config_readl(bdf, ofs);
             if (val != 0) {
                 size = (~(val & ~0xf)) + 1;
-                if (val & PCI_ADDRESS_SPACE_IO)
+                if (val & PCI_BASE_ADDRESS_SPACE_IO)
                     paddr = &pci_bios_io_addr;
                 else if (size >= 0x04000000)
                     paddr = &pci_bios_bigmem_addr;
@@ -180,11 +182,14 @@ static void pci_bios_init_device(u16 bdf)
     if (vendor_id == PCI_VENDOR_ID_INTEL
         && device_id == PCI_DEVICE_ID_INTEL_82371AB_3) {
         /* PIIX4 Power Management device (for ACPI) */
-        u32 pm_io_base = BUILD_PM_IO_BASE;
-        pci_config_writel(bdf, 0x40, pm_io_base | 1);
+
+        if (CONFIG_KVM)
+            // acpi sci is hardwired to 9
+            pci_config_writeb(bdf, PCI_INTERRUPT_LINE, 9);
+
+        pci_config_writel(bdf, 0x40, PORT_ACPI_PM_BASE | 1);
         pci_config_writeb(bdf, 0x80, 0x01); /* enable PM io space */
-        u32 smb_io_base = BUILD_SMB_IO_BASE;
-        pci_config_writel(bdf, 0x90, smb_io_base | 1);
+        pci_config_writel(bdf, 0x90, PORT_SMB_BASE | 1);
         pci_config_writeb(bdf, 0xd2, 0x09); /* enable SMBus io space */
     }
 }
@@ -198,15 +203,15 @@ pci_bios_setup(void)
 
     pci_bios_io_addr = 0xc000;
     pci_bios_mem_addr = 0xf0000000;
-    pci_bios_bigmem_addr = GET_EBDA(ram_size);
+    pci_bios_bigmem_addr = RamSize;
     if (pci_bios_bigmem_addr < 0x90000000)
         pci_bios_bigmem_addr = 0x90000000;
 
     int bdf, max;
-    foreachpci(bdf, max, 0) {
+    foreachpci(bdf, max) {
         pci_bios_init_bridges(bdf);
     }
-    foreachpci(bdf, max, 0) {
+    foreachpci(bdf, max) {
         pci_bios_init_device(bdf);
     }
 }