Set the PCI base address to 0xf0000000.

[seabios.git] / src / pciinit.c

diff --git a/src/pciinit.c b/src/pciinit.c
index c228ea060998a67de2196312f738f791124832d5..6a2f3711495f6105fed3c1ef4ea456d5355714aa 100644 (file)
--- a/src/pciinit.c
+++ b/src/pciinit.c
@@ -3,7 +3,7 @@
 // Copyright (C) 2008  Kevin O'Connor <kevin@koconnor.net>
 // Copyright (C) 2006 Fabrice Bellard
 //
-// This file may be distributed under the terms of the GNU GPLv3 license.
+// This file may be distributed under the terms of the GNU LGPLv3 license.
 
 #include "util.h" // dprintf
 #include "pci.h" // pci_config_readl
@@ -18,7 +18,9 @@ static u32 pci_bios_io_addr;
 static u32 pci_bios_mem_addr;
 static u32 pci_bios_bigmem_addr;
 /* host irqs corresponding to PCI irqs A-D */
-static u8 pci_irqs[4] = { 11, 9, 11, 9 };
+static u8 pci_irqs[4] = {
+    10, 10, 11, 11
+};
 
 static void pci_set_io_region_addr(u16 bdf, int region_num, u32 addr)
 {
@@ -71,7 +73,7 @@ static void pci_bios_init_bridges(u16 bdf)
 
         elcr[0] = 0x00;
         elcr[1] = 0x00;
-        for(i = 0; i < 4; i++) {
+        for (i = 0; i < 4; i++) {
             irq = pci_irqs[i];
             /* set to trigger level */
             elcr[irq >> 3] |= (1 << (irq & 7));
@@ -96,7 +98,7 @@ static void pci_bios_init_device(u16 bdf)
     device_id = pci_config_readw(bdf, PCI_DEVICE_ID);
     dprintf(1, "PCI: bus=%d devfn=0x%02x: vendor_id=0x%04x device_id=0x%04x\n"
             , pci_bdf_to_bus(bdf), pci_bdf_to_devfn(bdf), vendor_id, device_id);
-    switch(class) {
+    switch (class) {
     case PCI_CLASS_STORAGE_IDE:
         if (vendor_id == PCI_VENDOR_ID_INTEL
             && (device_id == PCI_DEVICE_ID_INTEL_82371SB_1
@@ -113,12 +115,6 @@ static void pci_bios_init_device(u16 bdf)
             pci_set_io_region_addr(bdf, 3, 0x374);
         }
         break;
-    case PCI_CLASS_DISPLAY_VGA:
-        if (vendor_id != 0x1234)
-            goto default_map;
-        /* VGA: map frame buffer to default Bochs VBE address */
-        pci_set_io_region_addr(bdf, 0, 0xE0000000);
-        break;
     case PCI_CLASS_SYSTEM_PIC:
         /* PIC */
         if (vendor_id == PCI_VENDOR_ID_IBM) {
@@ -176,6 +172,10 @@ static void pci_bios_init_device(u16 bdf)
     if (vendor_id == PCI_VENDOR_ID_INTEL
         && device_id == PCI_DEVICE_ID_INTEL_82371AB_3) {
         /* PIIX4 Power Management device (for ACPI) */
+
+        // acpi sci is hardwired to 9
+        pci_config_writeb(bdf, PCI_INTERRUPT_LINE, 9);
+
         pci_config_writel(bdf, 0x40, PORT_ACPI_PM_BASE | 1);
         pci_config_writeb(bdf, 0x80, 0x01); /* enable PM io space */
         pci_config_writel(bdf, 0x90, PORT_SMB_BASE | 1);
@@ -184,15 +184,17 @@ static void pci_bios_init_device(u16 bdf)
 }
 
 void
-pci_bios_setup(void)
+pci_setup(void)
 {
     if (CONFIG_COREBOOT)
         // Already done by coreboot.
         return;
 
+    dprintf(3, "pci setup\n");
+
     pci_bios_io_addr = 0xc000;
     pci_bios_mem_addr = 0xf0000000;
-    pci_bios_bigmem_addr = GET_EBDA(ram_size);
+    pci_bios_bigmem_addr = RamSize;
     if (pci_bios_bigmem_addr < 0x90000000)
         pci_bios_bigmem_addr = 0x90000000;