Synch pci ids and registers with Linux kernel source.

[seabios.git] / src / pciinit.c

diff --git a/src/pciinit.c b/src/pciinit.c
index 303f581ef5c48892f2d96d408f76594d7d61db38..66ff76aa9e1047e1a628bd7052b553a83a730416 100644 (file)
--- a/src/pciinit.c
+++ b/src/pciinit.c
@@ -7,6 +7,9 @@
 
 #include "util.h" // dprintf
 #include "pci.h" // PCIDevice
+#include "biosvar.h" // GET_EBDA
+#include "pci_ids.h" // PCI_VENDOR_ID_INTEL
+#include "pci_regs.h" // PCI_COMMAND
 
 #define PCI_ADDRESS_SPACE_MEM          0x00
 #define PCI_ADDRESS_SPACE_IO           0x01
@@ -15,8 +18,6 @@
 #define PCI_ROM_SLOT 6
 #define PCI_NUM_REGIONS 7
 
-#define PCI_DEVICES_MAX 64
-
 static u32 pci_bios_io_addr;
 static u32 pci_bios_mem_addr;
 static u32 pci_bios_bigmem_addr;
@@ -67,11 +68,13 @@ static void pci_bios_init_bridges(PCIDevice d)
     vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
     device_id = pci_config_readw(d, PCI_DEVICE_ID);
 
-    if (vendor_id == 0x8086 && device_id == 0x7000) {
+    if (vendor_id == PCI_VENDOR_ID_INTEL
+        && (device_id == PCI_DEVICE_ID_INTEL_82371SB_0
+            || device_id == PCI_DEVICE_ID_INTEL_82371AB_0)) {
         int i, irq;
         u8 elcr[2];
 
-        /* PIIX3 bridge */
+        /* PIIX3/PIIX4 PCI to ISA bridge */
 
         elcr[0] = 0x00;
         elcr[1] = 0x00;
@@ -84,7 +87,7 @@ static void pci_bios_init_bridges(PCIDevice d)
         }
         outb(elcr[0], 0x4d0);
         outb(elcr[1], 0x4d1);
-        dprintf(1, "PIIX3 init: elcr=%02x %02x\n",
+        dprintf(1, "PIIX3/PIIX4 init: elcr=%02x %02x\n",
                 elcr[0], elcr[1]);
     }
 }
@@ -102,8 +105,10 @@ static void pci_bios_init_device(PCIDevice d)
             d.bus, d.devfn, vendor_id, device_id);
     switch(class) {
     case 0x0101:
-        if (vendor_id == 0x8086 && device_id == 0x7010) {
-            /* PIIX3 IDE */
+        if (vendor_id == PCI_VENDOR_ID_INTEL
+            && (device_id == PCI_DEVICE_ID_INTEL_82371SB_1
+                || device_id == PCI_DEVICE_ID_INTEL_82371AB)) {
+            /* PIIX3/PIIX4 IDE */
             pci_config_writew(d, 0x40, 0x8000); // enable IDE0
             pci_config_writew(d, 0x42, 0x8000); // enable IDE1
             goto default_map;
@@ -123,7 +128,7 @@ static void pci_bios_init_device(PCIDevice d)
         break;
     case 0x0800:
         /* PIC */
-        if (vendor_id == 0x1014) {
+        if (vendor_id == PCI_VENDOR_ID_IBM) {
             /* IBM */
             if (device_id == 0x0046 || device_id == 0xFFFF) {
                 /* MPIC & MPIC2 */
@@ -132,7 +137,7 @@ static void pci_bios_init_device(PCIDevice d)
         }
         break;
     case 0xff00:
-        if (vendor_id == 0x0106b &&
+        if (vendor_id == PCI_VENDOR_ID_APPLE &&
             (device_id == 0x0017 || device_id == 0x0022)) {
             /* macio bridge */
             pci_set_io_region_addr(d, 0, 0x80800000);
@@ -143,7 +148,7 @@ static void pci_bios_init_device(PCIDevice d)
         /* default memory mappings */
         for(i = 0; i < PCI_NUM_REGIONS; i++) {
             int ofs;
-            u32 val, size ;
+            u32 val, size;
 
             if (i == PCI_ROM_SLOT)
                 ofs = 0x30;
@@ -159,7 +164,7 @@ static void pci_bios_init_device(PCIDevice d)
                     paddr = &pci_bios_bigmem_addr;
                 else
                     paddr = &pci_bios_mem_addr;
-                *paddr = (*paddr + size - 1) & ~(size - 1);
+                *paddr = ALIGN(*paddr, size);
                 pci_set_io_region_addr(d, i, *paddr);
                 *paddr += size;
             }
@@ -175,7 +180,8 @@ static void pci_bios_init_device(PCIDevice d)
         pci_config_writeb(d, PCI_INTERRUPT_LINE, pic_irq);
     }
 
-    if (vendor_id == 0x8086 && device_id == 0x7113) {
+    if (vendor_id == PCI_VENDOR_ID_INTEL
+        && device_id == PCI_DEVICE_ID_INTEL_82371AB_3) {
         /* PIIX4 Power Management device (for ACPI) */
         u32 pm_io_base = BUILD_PM_IO_BASE;
         pci_config_writel(d, 0x40, pm_io_base | 1);