#include "biosvar.h" // GET_EBDA
#include "pci_ids.h" // PCI_VENDOR_ID_INTEL
#include "pci_regs.h" // PCI_COMMAND
-#include "dev-i440fx.h"
+#include "xen.h" // usingXen
#define PCI_ROM_SLOT 6
#define PCI_NUM_REGIONS 7
static void pci_bios_init_device_in_bus(int bus);
-static u32 pci_bios_io_addr;
-static u32 pci_bios_mem_addr;
-static u32 pci_bios_prefmem_addr;
+static struct pci_region pci_bios_io_region;
+static struct pci_region pci_bios_mem_region;
+static struct pci_region pci_bios_prefmem_region;
+
/* host irqs corresponding to PCI irqs A-D */
const u8 pci_irqs[4] = {
10, 10, 11, 11
static void pci_set_io_region_addr(u16 bdf, int region_num, u32 addr)
{
- u32 ofs, old_addr;
+ u32 ofs;
ofs = pci_bar(bdf, region_num);
- old_addr = pci_config_readl(bdf, ofs);
-
pci_config_writel(bdf, ofs, addr);
dprintf(1, "region %d: 0x%08x\n", region_num, addr);
}
*/
static int pci_bios_allocate_region(u16 bdf, int region_num)
{
- u32 *paddr;
+ struct pci_region *r;
u32 ofs = pci_bar(bdf, region_num);
u32 old = pci_config_readl(bdf, ofs);
u32 size = (~(val & mask)) + 1;
if (val != 0) {
+ const char *type;
+ const char *msg;
if (val & PCI_BASE_ADDRESS_SPACE_IO) {
- paddr = &pci_bios_io_addr;
- if (ALIGN(*paddr, size) + size >= 64 * 1024) {
- dprintf(1,
- "io region of (bdf 0x%x bar %d) can't be mapped.\n",
- bdf, region_num);
- size = 0;
- }
+ r = &pci_bios_io_region;
+ type = "io";
+ msg = "";
} else if ((val & PCI_BASE_ADDRESS_MEM_PREFETCH) &&
- /* keep behaviour on bus = 0 */
- pci_bdf_to_bus(bdf) != 0 &&
- /* If pci_bios_prefmem_addr == 0, keep old behaviour */
- pci_bios_prefmem_addr != 0) {
- paddr = &pci_bios_prefmem_addr;
- if (ALIGN(*paddr, size) + size >= BUILD_PCIPREFMEM_END) {
- dprintf(1,
- "prefmem region of (bdf 0x%x bar %d) can't be mapped. "
- "decrease BUILD_PCIMEM_SIZE and recompile. size %x\n",
- bdf, region_num, BUILD_PCIPREFMEM_SIZE);
- size = 0;
- }
+ /* keep behaviour on bus = 0 */
+ pci_bdf_to_bus(bdf) != 0 &&
+ /* If pci_bios_prefmem_addr == 0, keep old behaviour */
+ pci_region_addr(&pci_bios_prefmem_region) != 0) {
+ r = &pci_bios_prefmem_region;
+ type = "prefmem";
+ msg = "decrease BUILD_PCIMEM_SIZE and recompile. size %x";
} else {
- paddr = &pci_bios_mem_addr;
- if (ALIGN(*paddr, size) + size >= BUILD_PCIMEM_END) {
- dprintf(1,
- "mem region of (bdf 0x%x bar %d) can't be mapped. "
- "increase BUILD_PCIMEM_SIZE and recompile. size %x\n",
- bdf, region_num, BUILD_PCIMEM_SIZE);
- size = 0;
- }
+ r = &pci_bios_mem_region;
+ type = "mem";
+ msg = "increase BUILD_PCIMEM_SIZE and recompile.";
}
- if (size > 0) {
- *paddr = ALIGN(*paddr, size);
- pci_set_io_region_addr(bdf, region_num, *paddr);
- *paddr += size;
+ u32 addr = pci_region_alloc(r, size);
+ if (addr > 0) {
+ pci_set_io_region_addr(bdf, region_num, addr);
+ } else {
+ size = 0;
+ dprintf(1,
+ "%s region of (bdf 0x%x bar %d) can't be mapped. "
+ "%s size %x\n",
+ type, bdf, region_num, msg, pci_region_size(r));
}
}
int is_64bit = !(val & PCI_BASE_ADDRESS_SPACE_IO) &&
(val & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == PCI_BASE_ADDRESS_MEM_TYPE_64;
- if (is_64bit) {
- if (size > 0) {
- pci_config_writel(bdf, ofs + 4, 0);
- } else {
- pci_config_writel(bdf, ofs + 4, ~0);
- }
+ if (is_64bit && size > 0) {
+ pci_config_writel(bdf, ofs + 4, 0);
}
return is_64bit;
}
-void pci_bios_allocate_regions(u16 bdf, void *arg)
+static void pci_bios_allocate_regions(struct pci_device *pci, void *arg)
{
int i;
for (i = 0; i < PCI_NUM_REGIONS; i++) {
- int is_64bit = pci_bios_allocate_region(bdf, i);
+ int is_64bit = pci_bios_allocate_region(pci->bdf, i);
if (is_64bit){
i++;
}
return (irq_num + slot_addend) & 3;
}
+/* PIIX3/PIIX4 PCI to ISA bridge */
+static void piix_isa_bridge_init(struct pci_device *pci, void *arg)
+{
+ int i, irq;
+ u8 elcr[2];
+
+ elcr[0] = 0x00;
+ elcr[1] = 0x00;
+ for (i = 0; i < 4; i++) {
+ irq = pci_irqs[i];
+ /* set to trigger level */
+ elcr[irq >> 3] |= (1 << (irq & 7));
+ /* activate irq remapping in PIIX */
+ pci_config_writeb(pci->bdf, 0x60 + i, irq);
+ }
+ outb(elcr[0], 0x4d0);
+ outb(elcr[1], 0x4d1);
+ dprintf(1, "PIIX3/PIIX4 init: elcr=%02x %02x\n", elcr[0], elcr[1]);
+}
+
static const struct pci_device_id pci_isa_bridge_tbl[] = {
/* PIIX3/PIIX4 PCI to ISA bridge */
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0,
#define PCI_PREF_MEMORY_ALIGN (1UL << 20)
#define PCI_PREF_MEMORY_SHIFT 16
-static void pci_bios_init_device_bridge(u16 bdf, void *arg)
+static void pci_bios_init_device_bridge(struct pci_device *pci, void *arg)
{
+ u16 bdf = pci->bdf;
pci_bios_allocate_region(bdf, 0);
pci_bios_allocate_region(bdf, 1);
pci_bios_allocate_region(bdf, PCI_ROM_SLOT);
- u32 io_old = pci_bios_io_addr;
- u32 mem_old = pci_bios_mem_addr;
- u32 prefmem_old = pci_bios_prefmem_addr;
+ u32 io_old = pci_region_addr(&pci_bios_io_region);
+ u32 mem_old = pci_region_addr(&pci_bios_mem_region);
+ u32 prefmem_old = pci_region_addr(&pci_bios_prefmem_region);
/* IO BASE is assumed to be 16 bit */
- pci_bios_io_addr = ALIGN(pci_bios_io_addr, PCI_IO_ALIGN);
- pci_bios_mem_addr = ALIGN(pci_bios_mem_addr, PCI_MEMORY_ALIGN);
- pci_bios_prefmem_addr =
- ALIGN(pci_bios_prefmem_addr, PCI_PREF_MEMORY_ALIGN);
+ if (pci_region_align(&pci_bios_io_region, PCI_IO_ALIGN) == 0) {
+ pci_region_disable(&pci_bios_io_region);
+ }
+ if (pci_region_align(&pci_bios_mem_region, PCI_MEMORY_ALIGN) == 0) {
+ pci_region_disable(&pci_bios_mem_region);
+ }
+ if (pci_region_align(&pci_bios_prefmem_region,
+ PCI_PREF_MEMORY_ALIGN) == 0) {
+ pci_region_disable(&pci_bios_prefmem_region);
+ }
- u32 io_base = pci_bios_io_addr;
- u32 mem_base = pci_bios_mem_addr;
- u32 prefmem_base = pci_bios_prefmem_addr;
+ u32 io_base = pci_region_addr(&pci_bios_io_region);
+ u32 mem_base = pci_region_addr(&pci_bios_mem_region);
+ u32 prefmem_base = pci_region_addr(&pci_bios_prefmem_region);
u8 secbus = pci_config_readb(bdf, PCI_SECONDARY_BUS);
if (secbus > 0) {
pci_bios_init_device_in_bus(secbus);
}
- pci_bios_io_addr = ALIGN(pci_bios_io_addr, PCI_IO_ALIGN);
- pci_bios_mem_addr = ALIGN(pci_bios_mem_addr, PCI_MEMORY_ALIGN);
- pci_bios_prefmem_addr =
- ALIGN(pci_bios_prefmem_addr, PCI_PREF_MEMORY_ALIGN);
-
- u32 io_end = pci_bios_io_addr;
- if (io_end == io_base) {
- pci_bios_io_addr = io_old;
+ u32 io_end = pci_region_align(&pci_bios_io_region, PCI_IO_ALIGN);
+ if (io_end == 0) {
+ pci_region_revert(&pci_bios_io_region, io_old);
io_base = 0xffff;
io_end = 1;
}
pci_config_writeb(bdf, PCI_IO_LIMIT, (io_end - 1) >> PCI_IO_SHIFT);
pci_config_writew(bdf, PCI_IO_LIMIT_UPPER16, 0);
- u32 mem_end = pci_bios_mem_addr;
- if (mem_end == mem_base) {
- pci_bios_mem_addr = mem_old;
+ u32 mem_end = pci_region_align(&pci_bios_mem_region, PCI_MEMORY_ALIGN);
+ if (mem_end == 0) {
+ pci_region_revert(&pci_bios_mem_region, mem_old);
mem_base = 0xffffffff;
mem_end = 1;
}
pci_config_writew(bdf, PCI_MEMORY_BASE, mem_base >> PCI_MEMORY_SHIFT);
pci_config_writew(bdf, PCI_MEMORY_LIMIT, (mem_end -1) >> PCI_MEMORY_SHIFT);
- u32 prefmem_end = pci_bios_prefmem_addr;
- if (prefmem_end == prefmem_base) {
- pci_bios_prefmem_addr = prefmem_old;
+ u32 prefmem_end = pci_region_align(&pci_bios_prefmem_region,
+ PCI_PREF_MEMORY_ALIGN);
+ if (prefmem_end == 0) {
+ pci_region_revert(&pci_bios_prefmem_region, prefmem_old);
prefmem_base = 0xffffffff;
prefmem_end = 1;
}
pci_config_maskw(bdf, PCI_BRIDGE_CONTROL, 0, PCI_BRIDGE_CTL_SERR);
}
-static void storage_ide_init(u16 bdf, void *arg)
+static void storage_ide_init(struct pci_device *pci, void *arg)
{
+ u16 bdf = pci->bdf;
/* IDE: we map it as in ISA mode */
pci_set_io_region_addr(bdf, 0, PORT_ATA1_CMD_BASE);
pci_set_io_region_addr(bdf, 1, PORT_ATA1_CTRL_BASE);
pci_set_io_region_addr(bdf, 3, PORT_ATA2_CTRL_BASE);
}
-static void pic_ibm_init(u16 bdf, void *arg)
+/* PIIX3/PIIX4 IDE */
+static void piix_ide_init(struct pci_device *pci, void *arg)
+{
+ u16 bdf = pci->bdf;
+ pci_config_writew(bdf, 0x40, 0x8000); // enable IDE0
+ pci_config_writew(bdf, 0x42, 0x8000); // enable IDE1
+ pci_bios_allocate_regions(pci, NULL);
+}
+
+static void pic_ibm_init(struct pci_device *pci, void *arg)
{
/* PIC, IBM, MPIC & MPIC2 */
- pci_set_io_region_addr(bdf, 0, 0x80800000 + 0x00040000);
+ pci_set_io_region_addr(pci->bdf, 0, 0x80800000 + 0x00040000);
}
-static void apple_macio_init(u16 bdf, void *arg)
+static void apple_macio_init(struct pci_device *pci, void *arg)
{
/* macio bridge */
- pci_set_io_region_addr(bdf, 0, 0x80800000);
+ pci_set_io_region_addr(pci->bdf, 0, 0x80800000);
}
static const struct pci_device_id pci_class_tbl[] = {
PCI_DEVICE_END,
};
+/* PIIX4 Power Management device (for ACPI) */
+static void piix4_pm_init(struct pci_device *pci, void *arg)
+{
+ u16 bdf = pci->bdf;
+ // acpi sci is hardwired to 9
+ pci_config_writeb(bdf, PCI_INTERRUPT_LINE, 9);
+
+ pci_config_writel(bdf, 0x40, PORT_ACPI_PM_BASE | 1);
+ pci_config_writeb(bdf, 0x80, 0x01); /* enable PM io space */
+ pci_config_writel(bdf, 0x90, PORT_SMB_BASE | 1);
+ pci_config_writeb(bdf, 0xd2, 0x09); /* enable SMBus io space */
+}
+
static const struct pci_device_id pci_device_tbl[] = {
/* PIIX4 Power Management device (for ACPI) */
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3,
PCI_DEVICE_END,
};
-static void pci_bios_init_device(u16 bdf)
+static void pci_bios_init_device(struct pci_device *pci)
{
- int pin, pic_irq, vendor_id, device_id;
+ u16 bdf = pci->bdf;
+ int pin, pic_irq;
- vendor_id = pci_config_readw(bdf, PCI_VENDOR_ID);
- device_id = pci_config_readw(bdf, PCI_DEVICE_ID);
dprintf(1, "PCI: bus=%d devfn=0x%02x: vendor_id=0x%04x device_id=0x%04x\n"
- , pci_bdf_to_bus(bdf), pci_bdf_to_devfn(bdf), vendor_id, device_id);
- pci_init_device(pci_class_tbl, bdf, NULL);
+ , pci_bdf_to_bus(bdf), pci_bdf_to_devfn(bdf)
+ , pci->vendor, pci->device);
+ pci_init_device(pci_class_tbl, pci, NULL);
/* enable memory mappings */
pci_config_maskw(bdf, PCI_COMMAND, 0, PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
pci_config_writeb(bdf, PCI_INTERRUPT_LINE, pic_irq);
}
- pci_init_device(pci_device_tbl, bdf, NULL);
+ pci_init_device(pci_device_tbl, pci, NULL);
}
static void pci_bios_init_device_in_bus(int bus)
{
- int bdf, max;
- foreachpci_in_bus(bdf, max, bus) {
- pci_bios_init_device(bdf);
+ struct pci_device *pci;
+ foreachpci(pci) {
+ u8 pci_bus = pci_bdf_to_bus(pci->bdf);
+ if (pci_bus < bus)
+ continue;
+ if (pci_bus > bus)
+ break;
+ pci_bios_init_device(pci);
}
}
static void
pci_bios_init_bus_rec(int bus, u8 *pci_bus)
{
- int bdf, max;
+ int bdf;
u16 class;
dprintf(1, "PCI: %s bus = 0x%x\n", __func__, bus);
/* prevent accidental access to unintended devices */
- foreachpci_in_bus(bdf, max, bus) {
+ foreachbdf(bdf, bus) {
class = pci_config_readw(bdf, PCI_CLASS_DEVICE);
if (class == PCI_CLASS_BRIDGE_PCI) {
pci_config_writeb(bdf, PCI_SECONDARY_BUS, 255);
}
}
- foreachpci_in_bus(bdf, max, bus) {
+ foreachbdf(bdf, bus) {
class = pci_config_readw(bdf, PCI_CLASS_DEVICE);
if (class != PCI_CLASS_BRIDGE_PCI) {
continue;
void
pci_setup(void)
{
- if (CONFIG_COREBOOT)
- // Already done by coreboot.
+ if (CONFIG_COREBOOT || usingXen()) {
+ // PCI setup already done by coreboot or Xen - just do probe.
+ pci_probe();
return;
+ }
dprintf(3, "pci setup\n");
- pci_bios_io_addr = 0xc000;
- pci_bios_mem_addr = BUILD_PCIMEM_START;
- pci_bios_prefmem_addr = BUILD_PCIPREFMEM_START;
+ pci_region_init(&pci_bios_io_region, 0xc000, 64 * 1024 - 1);
+ pci_region_init(&pci_bios_mem_region,
+ BUILD_PCIMEM_START, BUILD_PCIMEM_END - 1);
+ pci_region_init(&pci_bios_prefmem_region,
+ BUILD_PCIPREFMEM_START, BUILD_PCIPREFMEM_END - 1);
pci_bios_init_bus();
- int bdf, max;
- foreachpci(bdf, max) {
- pci_init_device(pci_isa_bridge_tbl, bdf, NULL);
+ pci_probe();
+
+ struct pci_device *pci;
+ foreachpci(pci) {
+ pci_init_device(pci_isa_bridge_tbl, pci, NULL);
}
pci_bios_init_device_in_bus(0 /* host bus */);
}
projects / seabios.git / blobdiff