#include "ioport.h" // outl
#include "util.h" // dprintf
#include "config.h" // CONFIG_*
+#include "farptr.h" // CONFIG_*
#include "pci_regs.h" // PCI_VENDOR_ID
-#include "farptr.h" // SET_VAR
+#include "pci_ids.h" // PCI_CLASS_DISPLAY_VGA
void pci_config_writel(u16 bdf, u32 addr, u32 val)
{
return inb(PORT_PCI_DATA + (addr & 3));
}
+void
+pci_config_maskw(u16 bdf, u32 addr, u16 off, u16 on)
+{
+ u16 val = pci_config_readw(bdf, addr);
+ val = (val & ~off) | on;
+ pci_config_writew(bdf, addr, val);
+}
+
+// Helper function for foreachpci() macro - return next device
int
pci_next(int bdf, int *pmax)
{
int max = *pmax;
for (;;) {
- if (bdf >= max)
- return -1;
+ if (bdf >= max) {
+ if (CONFIG_PCI_ROOT1 && bdf <= (CONFIG_PCI_ROOT1 << 8))
+ bdf = CONFIG_PCI_ROOT1 << 8;
+ else if (CONFIG_PCI_ROOT2 && bdf <= (CONFIG_PCI_ROOT2 << 8))
+ bdf = CONFIG_PCI_ROOT2 << 8;
+ else
+ return -1;
+ *pmax = max = bdf + 0x0100;
+ }
u16 v = pci_config_readw(bdf, PCI_VENDOR_ID);
if (v != 0x0000 && v != 0xffff)
return bdf;
}
+// Find a vga device with legacy address decoding enabled.
+int
+pci_find_vga(void)
+{
+ int bdf = 0x0000, max = 0x0100;
+ for (;;) {
+ if (bdf >= max) {
+ if (CONFIG_PCI_ROOT1 && bdf <= (CONFIG_PCI_ROOT1 << 8))
+ bdf = CONFIG_PCI_ROOT1 << 8;
+ else if (CONFIG_PCI_ROOT2 && bdf <= (CONFIG_PCI_ROOT2 << 8))
+ bdf = CONFIG_PCI_ROOT2 << 8;
+ else
+ return -1;
+ max = bdf + 0x0100;
+ }
+
+ u16 cls = pci_config_readw(bdf, PCI_CLASS_DEVICE);
+ if (cls == 0x0000 || cls == 0xffff) {
+ // Device not present.
+ if (pci_bdf_to_fn(bdf) == 0)
+ bdf += 8;
+ else
+ bdf += 1;
+ continue;
+ }
+ if (cls == PCI_CLASS_DISPLAY_VGA) {
+ u16 cmd = pci_config_readw(bdf, PCI_COMMAND);
+ if (cmd & PCI_COMMAND_IO && cmd & PCI_COMMAND_MEMORY)
+ // Found active vga card
+ return bdf;
+ }
+
+ // Check if device is a bridge.
+ u8 hdr = pci_config_readb(bdf, PCI_HEADER_TYPE);
+ u8 ht = hdr & 0x7f;
+ if (ht == PCI_HEADER_TYPE_BRIDGE || ht == PCI_HEADER_TYPE_CARDBUS) {
+ u32 ctrl = pci_config_readb(bdf, PCI_BRIDGE_CONTROL);
+ if (ctrl & PCI_BRIDGE_CTL_VGA) {
+ // Found a VGA enabled bridge.
+ u32 pbus = pci_config_readl(bdf, PCI_PRIMARY_BUS);
+ bdf = (pbus & 0xff00);
+ max = bdf + 0x100;
+ continue;
+ }
+ }
+
+ if (pci_bdf_to_fn(bdf) == 0 && (hdr & 0x80) == 0)
+ // Last found device wasn't a multi-function device - skip to
+ // the next device.
+ bdf += 8;
+ else
+ bdf += 1;
+ }
+}
+
// Search for a device with the specified vendor and device ids.
int
pci_find_device(u16 vendid, u16 devid)
int bdf, max;
foreachpci(bdf, max) {
u32 v = pci_config_readl(bdf, PCI_VENDOR_ID);
- if (v != id)
- continue;
- // Found it.
- return bdf;
+ if (v == id)
+ return bdf;
}
return -1;
}
int bdf, max;
foreachpci(bdf, max) {
u16 v = pci_config_readw(bdf, PCI_CLASS_DEVICE);
- if (v != classid)
- continue;
- // Found it.
- return bdf;
+ if (v == classid)
+ return bdf;
}
return -1;
}
+
+int pci_init_device(const struct pci_device_id *ids, u16 bdf, void *arg)
+{
+ u16 vendor_id = pci_config_readw(bdf, PCI_VENDOR_ID);
+ u16 device_id = pci_config_readw(bdf, PCI_DEVICE_ID);
+ u16 class = pci_config_readw(bdf, PCI_CLASS_DEVICE);
+
+ while (ids->vendid || ids->class_mask) {
+ if ((ids->vendid == PCI_ANY_ID || ids->vendid == vendor_id) &&
+ (ids->devid == PCI_ANY_ID || ids->devid == device_id) &&
+ !((ids->class ^ class) & ids->class_mask)) {
+ if (ids->func) {
+ ids->func(bdf, arg);
+ }
+ return 0;
+ }
+ ids++;
+ }
+ return -1;
+}
+
+int pci_find_init_device(const struct pci_device_id *ids, void *arg)
+{
+ int bdf, max;
+
+ foreachpci(bdf, max) {
+ if (pci_init_device(ids, bdf, arg) == 0) {
+ return bdf;
+ }
+ }
+ return -1;
+}
+
+void
+pci_reboot(void)
+{
+ u8 v = inb(PORT_PCI_REBOOT) & ~6;
+ outb(v|2, PORT_PCI_REBOOT); /* Request hard reset */
+ udelay(50);
+ outb(v|6, PORT_PCI_REBOOT); /* Actually do the reset */
+ udelay(50);
+}
+
+// helper functions to access pci mmio bars from real mode
+
+u32 VISIBLE32FLAT
+pci_readl_32(u32 addr)
+{
+ dprintf(3, "32: pci read : %x\n", addr);
+ return readl((void*)addr);
+}
+
+u32 pci_readl(u32 addr)
+{
+ if (MODESEGMENT) {
+ dprintf(3, "16: pci read : %x\n", addr);
+ extern void _cfunc32flat_pci_readl_32(u32 addr);
+ return call32(_cfunc32flat_pci_readl_32, addr, -1);
+ } else {
+ return pci_readl_32(addr);
+ }
+}
+
+struct reg32 {
+ u32 addr;
+ u32 data;
+};
+
+void VISIBLE32FLAT
+pci_writel_32(struct reg32 *reg32)
+{
+ dprintf(3, "32: pci write: %x, %x (%p)\n", reg32->addr, reg32->data, reg32);
+ writel((void*)(reg32->addr), reg32->data);
+}
+
+void pci_writel(u32 addr, u32 val)
+{
+ struct reg32 reg32 = { .addr = addr, .data = val };
+ if (MODESEGMENT) {
+ dprintf(3, "16: pci write: %x, %x (%x:%p)\n",
+ reg32.addr, reg32.data, GET_SEG(SS), ®32);
+ void *flatptr = MAKE_FLATPTR(GET_SEG(SS), ®32);
+ extern void _cfunc32flat_pci_writel_32(struct reg32 *reg32);
+ call32(_cfunc32flat_pci_writel_32, (u32)flatptr, -1);
+ } else {
+ pci_writel_32(®32);
+ }
+}
projects / seabios.git / blobdiff