#include <../northbridge/via/vx800/vx800.h>
#include <arch/io.h>
-#include <arch/pci_rawops.h>
+#include "pci_rawops.h"
static const struct VIA_PCI_REG_INIT_TABLE mSbStage1InitTbl[] = {
// Combine Stage1 registers
0x00, 0xFF, NB_PXPTRF_REG(0x84), 0x00, 0x28,
0x00, 0xFF, NB_PXPTRF_REG(0x85), 0x00, 0xC0,
0x00, 0xFF, NB_MSGC_REG(0xA3), 0x00, 0x01, // RWAKEEN
-// 0x00, 0xFF, NB_PXPTRF_REG(0x64), 0x40, 0x00, //RTDNP2B32EN
+// 0x00, 0xFF, NB_PXPTRF_REG(0x64), 0x40, 0x00, //RTDNP2B32EN
0x00, 0xFF, NB_PXPTRF_REG(0xF3), 0xFC, 0x20,
0x00, 0xFF, NB_PXPTRF_REG(0x85), 0x00, 0x00, //RP2P1ABORT
-// fine-tune
+// fine-tune
// If no settings, C7 will hang or reboot in XP, but CN will not.
0x00, 0xFF, NB_HOST_REG(0x51), 0x84, 0x00,
0x00, 0xFF, NB_HOST_REG(0x52), 0x0F, 0x03,
0x00, 0xFF, NB_HOST_REG(0x5C), 0x10, 0x10,
0x00, 0xFF, NB_HOST_REG(0x5F), 0x0E, 0x08,
0x00, 0xFF, NB_HOST_REG(0x92), 0xFF, 0x04, // ACPI Base addr
- 0x00, 0xFF, NB_HOST_REG(0x97), 0x01, 0x01, // APIC MSI
- 0x00, 0xFF, NB_HOST_REG(0x99), 0x02, 0x00, // APIC MSI
+ 0x00, 0xFF, NB_HOST_REG(0x97), 0x01, 0x01, // APIC MSI
+ 0x00, 0xFF, NB_HOST_REG(0x99), 0x02, 0x00, // APIC MSI
//GTL
0x00, 0xFF, NB_HOST_REG(0x73), 0xFF, 0x66,
0x00, 0xFF, NB_HOST_REG(0xB2), 0xFF, 0x33,
0x00, 0xFF, SB_LPC_REG(0x67), 0x03, 0x01,
- 0x00, 0xFF, SB_LPC_REG(0x50), 0x7E, 0x00, // Setting PCI device enable
- 0x00, 0xFF, SB_LPC_REG(0x51), 0xD0, 0x00, // Setting PCI device enable
- 0x00, 0xFF, SB_VLINK_REG(0xD1), 0x04, 0x00, // Setting HDAC enable
+ 0x00, 0xFF, SB_LPC_REG(0x50), 0x7E, 0x00, // Setting PCI device enable
+ 0x00, 0xFF, SB_LPC_REG(0x51), 0xD0, 0x00, // Setting PCI device enable
+ 0x00, 0xFF, SB_VLINK_REG(0xD1), 0x04, 0x00, // Setting HDAC enable
{0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // End of Table
};
device_t_raw rawdevice = 0;
u8 sbchiprev;
rawdevice = PCI_RAWDEV(0, 0x11, 0);
- // Set the PMIO base io address
+ // Set the PMIO base io address
pci_rawmodify_config16(rawdevice, 0x88, VX800_ACPI_IO_BASE,
0xff80);
// Enable PMIO
// Get SB Revision
sbchiprev = pci_rawread_config8(rawdevice, 0xf6);
- printk_debug("SB chip revision =%x\n", sbchiprev);
+ printk(BIOS_DEBUG, "SB chip revision =%x\n", sbchiprev);
// Fill Register Table
via_pci_inittable(sbchiprev, mSbStage1InitTbl);
u32 subid = 0;
rawdevice = PCI_RAWDEV(0, 0, 4);
nbchiprev = pci_rawread_config8(rawdevice, 0xf6);
- printk_debug("NB chip revision =%x\n", nbchiprev);
+ printk(BIOS_DEBUG, "NB chip revision =%x\n", nbchiprev);
via_pci_inittable(nbchiprev, mNbStage2InitTable);
pci_rawmodify_config8(PCI_RAWDEV(0, 0xf, 0), 0x45, 0x80, 0x00);
pci_rawmodify_config8(PCI_RAWDEV(0, 0xf, 0), 0x40, 0x02, 0x00);
- pci_rawmodify_config8(PCI_RAWDEV(0, 0xf, 0), 0x09, 0x00, 0x05); //COMPATIBLE MODE
-// pci_rawmodify_config8(PCI_RAWDEV(0, 0xf, 0), 0x09, 0x05, 0x05);//native MODE
+ pci_rawmodify_config8(PCI_RAWDEV(0, 0xf, 0), 0x09, 0x00, 0x05); //COMPATIBLE MODE
+// pci_rawmodify_config8(PCI_RAWDEV(0, 0xf, 0), 0x09, 0x05, 0x05);//native MODE
via_pci_inittable(sbchiprev, IDEC_INIT);
}
// Get Chipset Revision
EHCIRevision =
pci_rawread_config8(PCI_RAWDEV(0, 0x10, 4), 0xF6);
- printk_debug("EHCI Revision =%x\n", EHCIRevision);
+ printk(BIOS_DEBUG, "EHCI Revision =%x\n", EHCIRevision);
via_pci_inittable(EHCIRevision, mEHCIInitTable);
}
}
0x00, 0xFF, SB_LPC_REG(0xE2), 0x00, 0xEA,
0x00, 0xFF, SB_LPC_REG(0xE7), 0x00, 0x80,
- {0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // End of Table
+ {0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // End of Table
};
void InitPMU(u8 sbchiprev)
rawdevice = PCI_RAWDEV(0, 11, 0);
sbchiprev = pci_rawread_config8(rawdevice, 0xf6);
- printk_debug("SB chip revision =%x\n", sbchiprev);
+ printk(BIOS_DEBUG, "SB chip revision =%x\n", sbchiprev);
//SBBasicInit
via_pci_inittable(sbchiprev, mBusControllerInitTable);
void init_VIA_chipset(void)
{
- printk_debug("In: init_VIA_chipset\n");
- //1.nbstage1 is done in raminit.
- //2.sbstage1
+ printk(BIOS_DEBUG, "In: init_VIA_chipset\n");
+ //1.nbstage1 is done in raminit.
+ //2.sbstage1
AcpiInit();
//3.nbstage2
Stage2NbInit();
//5.open hdac
pci_rawmodify_config32(PCI_RAWDEV(0, 0x11, 7), 0xd1, 0, 0x04);
- printk_debug("End: init_VIA_chipset\n");
+ printk(BIOS_DEBUG, "End: init_VIA_chipset\n");
}
/**
* @brief Main function of the DRAM part of coreboot.
*
- * Coreboot is divided into Pre-DRAM part and DRAM part.
+ * Coreboot is divided into Pre-DRAM part and DRAM part.
+ *
*
- *
* Device Enumeration:
- * In the dev_enumerate() phase,
+ * In the dev_enumerate() phase,
*/
void hardwaremain(int boot_complete)
u8 y, x;
init_VIA_chipset();
- printk_emerg("file '%s', line %d\n\n", __FILE__, __LINE__);
+ printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__);
#if 0
pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x51, 0x40, 0x40); //close CE-ATA (Consumer Electronics-ATA) and NFC
- //pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0x0, 0x40);//open USB Device Mode Enable
+ //pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0x0, 0x40);//open USB Device Mode Enable
pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0x40, 0x40); //close USB Device Mode
//pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0x04, 0x04);//close USB 1.1 UHCI Port 4-5
//pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0x00, 0x76);//open all usb and usb mode
//pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0x76, 0x76);//close all usb
- printk_info("=================SB 50h=%02x \n",
+ printk(BIOS_INFO, "=================SB 50h=%02x \n",
pci_rawread_config8(PCI_RAWDEV(0, 0x11, 0), 0x50));
/* FIXME: Is there a better way to handle this? */
init_timer();
- printk_emerg("file '%s', line %d\n\n", __FILE__, __LINE__);
+ printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__);
/* Find the devices we don't have hard coded knowledge about. */
dev_enumerate();
- printk_emerg("file '%s', line %d\n\n", __FILE__, __LINE__);
+ printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__);
#if 0
x = y = 0;
- printk_info("dump ehci3 \n");
+ printk(BIOS_INFO, "dump ehci3 \n");
for (; x < 16; x++) {
y = 0;
for (; y < 16; y++) {
- printk_info("%02x ",
+ printk(BIOS_INFO, "%02x ",
pci_rawread_config8(PCI_RAWDEV
(0, 0x10, 4),
x * 16 + y));
}
- printk_info("\n");
+ printk(BIOS_INFO, "\n");
}
#endif
post_code(0x66);
/* Now compute and assign the bus resources. */
dev_configure();
- printk_emerg("file '%s', line %d\n\n", __FILE__, __LINE__);
+ printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__);
#if 0
x = y = 0;
- printk_info("dump ehci3 \n");
+ printk(BIOS_INFO, "dump ehci3 \n");
for (; x < 16; x++) {
y = 0;
for (; y < 16; y++) {
- printk_info("%02x ",
+ printk(BIOS_INFO, "%02x ",
pci_rawread_config8(PCI_RAWDEV
(0, 0x10, 4),
x * 16 + y));
}
- printk_info("\n");
+ printk(BIOS_INFO, "\n");
}
#endif
post_code(0x88);
/* Now actually enable devices on the bus */
dev_enable();
- printk_emerg("file '%s', line %d\n\n", __FILE__, __LINE__);
+ printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__);
/* And of course initialize devices on the bus */
#if 0
x = y = 0;
- printk_info("dump ehci3 \n");
+ printk(BIOS_INFO, "dump ehci3 \n");
for (; x < 16; x++) {
y = 0;
for (; y < 16; y++) {
- printk_info("%02x ",
+ printk(BIOS_INFO, "%02x ",
pci_rawread_config8(PCI_RAWDEV
(0, 0x10, 4),
x * 16 + y));
}
- printk_info("\n");
+ printk(BIOS_INFO, "\n");
}
#endif
dev_initialize();
post_code(0x89);
- printk_emerg("file '%s', line %d\n\n", __FILE__, __LINE__);
+ printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__);
// pci_rawwrite_config16(PCI_RAWDEV(0, 0xf, 0), 0xBA, 0x0571);
#if 0
x = y = 0;
- printk_info("dump ehci3 \n");
+ printk(BIOS_INFO, "dump ehci3 \n");
for (; x < 16; x++) {
y = 0;
for (; y < 16; y++) {
- printk_info("%02x ",
+ printk(BIOS_INFO, "%02x ",
pci_rawread_config8(PCI_RAWDEV
(0, 0x10, 4),
x * 16 + y));
}
- printk_info("\n");
+ printk(BIOS_INFO, "\n");
}
#endif
pci_rawwrite_config8(PCI_RAWDEV(0, 0, 0), i, d0f0pcitable[i+0xcb]);
}
-
+
*/
/* RO reg
*/
-//boot ok, resume still err in linux
+//boot ok, resume still err in linux
#if 1
for (i = 0; i < 9; i++) {
pci_rawwrite_config8(PCI_RAWDEV(0, 0, 2), i + 0x50,
#if 1
-//d0f3
+//d0f3
/* */
// pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0x86, 0x3b); setting, my lspci is 0x29
//set bit4 cause the ide not be found
pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0xde, 0x00);
#endif
-//boot ok, resume err in coreboot
+//boot ok, resume err in coreboot
#if 1
for (i = 0; i < 99; i++) {
pci_rawwrite_config8(PCI_RAWDEV(0, 0, 4), i + 0x8d,
#if 1
-//boot ok, resume still err in linux
+//boot ok, resume still err in linux
for (i = 0; i < 160; i++) {
pci_rawwrite_config8(PCI_RAWDEV(0, 0, 5), i + 0x60,
d0f5pcitable[i]);
//6 is uart and dvp vcp, will have // HAVE no com1 ,and no gui show,textmode ok ,s3 sleep ok, resume fail
//7-18 is my familar part
- for (i = 7; i < 18; i++) { //sleep ok ,resume sleep err 2
+ for (i = 7; i < 18; i++) { //sleep ok ,resume sleep err 2
pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40,
d11f0pcitable[i]);
}
- for (i = 18; i < 21; i++) { //sleep ok , sleep err 1, resume
+ for (i = 18; i < 21; i++) { //sleep ok , sleep err 1, resume
pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40,
d11f0pcitable[i]);
}
#if 1
struct device *dev;
- printk_info("=========zjldump all devices...\n");
+ printk(BIOS_INFO, "=========zjldump all devices...\n");
for (dev = all_devices; dev; dev = dev->next) {
if (dev->path.type == DEVICE_PATH_PCI) {
- printk_debug("%s dump\n", dev_path(dev));
+ printk(BIOS_DEBUG, "%s dump\n", dev_path(dev));
x = y = 0;
for (; x < 16; x++) {
y = 0;
for (; y < 16; y++) {
- printk_info("%02x ",
+ printk(BIOS_INFO, "%02x ",
pci_read_config8(dev,
x *
16 +
y));
}
- printk_info("\n");
+ printk(BIOS_INFO, "\n");
}
}
- printk_info("\n");
+ printk(BIOS_INFO, "\n");
}
#endif
projects / coreboot.git / blobdiff