/*===================================================================
Function : DRAMRegInitValue()
-Precondition :
-Input :
+Precondition :
+Input :
DramAttr: pointer point to DRAM_SYS_ATTR which consist the DDR and Dimm information
in MotherBoard
Output : Void
// {0x79, 0x00, 0x8F },
{0x85, 0x00, 0x00},
// {0x90, 0x87, 0x78 },
- // {0x91, 0x00, 0x46 },
+ // {0x91, 0x00, 0x46 },
{0x40, 0x00, 0x00},
{0, 0, 0}
/*===================================================================
Function : DRAMInitializeProc()
-Precondition :
-Input :
+Precondition :
+Input :
DramAttr: pointer point to DRAM_SYS_ATTR which consist the DDR and Dimm information
in MotherBoard
Output : Void
#define EXIST_TEST_PATTERN 0x55555555
#define NOT_EXIST_TEST_PATTERN 0xAAAAAAAA
-BOOLEAN ChkForExistLowBank(void)
+static BOOLEAN ChkForExistLowBank(void)
{
u32 *Address, data32;
Address = (u32 *) 4;
*Address = EXIST_TEST_PATTERN;
- // _asm {WBINVD}
+ // _asm {WBINVD}
WaitMicroSec(100);
Address = (u32 *) 8;
data32 = *Address;
return TRUE;
}
-void InitDDR2CHC(DRAM_SYS_ATTR *DramAttr);
-void InitDDR2CHB(DRAM_SYS_ATTR *DramAttr);
-
void DRAMInitializeProc(DRAM_SYS_ATTR *DramAttr)
{
u8 shift, idx;
SetEndingAddr(DramAttr, idx, 0x10); /* Assume 1G size */
if (idx < 4) /* CHA init */
InitDDR2CHA(DramAttr); // temp wjb 2007/1 only for compiling
- // in the function InitDDR2,the parameter is no need
+ // in the function InitDDR2,the parameter is no need
Status = ChkForExistLowBank();
if (Status == TRUE) {
PRINT_DEBUG_MEM(" S\r");
/*===================================================================
Function : DRAMSetVRNUM()
-Precondition :
-Input :
+Precondition :
+Input :
DramAttr: pointer point to DRAM_SYS_ATTR which consist the DDR and Dimm information
in MotherBoard
PhyRank: Physical Rank number
/*===================================================================
Function : SetEndingAddr()
-Precondition :
-Input :
+Precondition :
+Input :
DramAttr: pointer point to DRAM_SYS_ATTR which consist the DDR and Dimm information
in MotherBoard
VirRank: Virtual Rank number
- Value: (value) add or subtract value to this and after banks
+ Value: (value) add or subtract value to this and after banks
Output : Void
-Purpose : Set ending address of virtual rank specified by VirRank
+Purpose : Set ending address of virtual rank specified by VirRank
===================================================================*/
void SetEndingAddr(DRAM_SYS_ATTR *DramAttr, u8 VirRank /* ending address
/*===================================================================
Function : InitDDR2()
-Precondition :
-Input :
+Precondition :
+Input :
DramAttr: pointer point to DRAM_SYS_ATTR which consist the DDR and Dimm information
in MotherBoard
Output : Void
/*===================================================================
Function : InitDDR2_CHB()
-Precondition :
-Input :
+Precondition :
+Input :
DramAttr: pointer point to DRAM_SYS_ATTR which consist the DDR and Dimm information
in MotherBoard
Output : Void
Purpose : Initialize DDR2 of CHB by standard sequence
-Reference :
+Reference :
===================================================================*/
/*// DLL: Enable Reset
static const u32 CHB_MRS_DLL_150[2] = { 0x00020200 | (1 << 20), 0x00000800 }; // with 150 ohm (A17=1, A9=1), (A11=1)(cpu address)
Data = 0x80;
pci_write_config8(MEMCTRL, 0x54, Data);
-
+
// step3.
//disable bank paging and multi page
Data=pci_read_config8(MEMCTRL, 0x69);
Data=pci_read_config8(MEMCTRL, 0xd3);
Data |= 0x80;
pci_write_config8(MEMCTRL, 0xd3, Data);
-
+
//step 4. Initialize CHB begin
Data=pci_read_config8(MEMCTRL, 0xd3);
Data |= 0x40;
pci_write_config8(MEMCTRL, 0xd3, Data);
-
+
//Step 5. NOP command enable
Data=pci_read_config8(MEMCTRL, 0xd7);
Data &= 0xC7;
Data |= 0x08;
pci_write_config8(MEMCTRL, 0xd7, Data);
-
+
//Step 6. issue a nop cycle,RegD3[7] 0 -> 1
Data=pci_read_config8(MEMCTRL, 0xd3);
Data &= 0x7F;
// Loop 200us
for (Idx = 0; Idx < 0x10; Idx++)
WaitMicroSec(10);
-
+
// Step 8.
// all banks precharge command enable
Data=pci_read_config8(MEMCTRL, 0xd7);
pci_write_config8(MEMCTRL, 0xd3, Data);
Data |= 0x80;
pci_write_config8(MEMCTRL, 0xd3, Data);
-
+
//step10. EMRS enable
Data=pci_read_config8(MEMCTRL, 0xd7);
Data &= 0xC7;
Data |= 0x00;
pci_write_config8(MEMCTRL, 0xd3, Data);
- //step 14. MSR DLL Reset
+ //step 14. MSR DLL Reset
AccessAddr = CHB_MRS_DLL_150[1] >> 3;
Data =(u8) (AccessAddr & 0xff);
pci_write_config8(MEMCTRL, 0xd9, Data);
Data |= 0x10;
pci_write_config8(MEMCTRL, 0xd7, Data);
-
+
// step17. issue precharge all cycle
Data=pci_read_config8(MEMCTRL, 0xd3);
Data &= 0x7F;
WaitMicroSec(200);
}
-
+
//step22. MSR enable
Data=pci_read_config8(MEMCTRL, 0xd7);
Data &= 0xC7;
Data |= 0x00;
pci_write_config8(MEMCTRL, 0xd3, Data);
-
+
//the SDRAM parameters.(Burst Length, CAS# Latency , Write recovery etc.)
//-------------------------------------------------------------
//Burst Length : really offset Rx6c[1]
pci_write_config8(MEMCTRL, 0xd3, Data);
Data |= 0x80;
pci_write_config8(MEMCTRL, 0xd3, Data);
-
+
//step 25. EMRS enable
Data=pci_read_config8(MEMCTRL, 0xd7);
Data &= 0xC7;
Data &= 0xC7;
Data |= 0x08;
pci_write_config8(MEMCTRL, 0xd3, Data);
-
+
//step 26. OCD default
AccessAddr = (CHB_OCD_Default_150ohm) >> 3;
pci_write_config8(MEMCTRL, 0xd3, Data);
Data |= 0x80;
pci_write_config8(MEMCTRL, 0xd3, Data);
-
+
//step 25. EMRS enable
Data=pci_read_config8(MEMCTRL, 0xd7);
Data &= 0xC7;
Data |= 0x00;
pci_write_config8(MEMCTRL, 0xd3, Data);
- //step 31. exit the initialization mode
+ //step 31. exit the initialization mode
Data=pci_read_config8(MEMCTRL, 0xd3);
Data &= 0xBF;
pci_write_config8(MEMCTRL, 0xd3, Data);
-
+
//step 32. Enable bank paging and multi page
Data=pci_read_config8(MEMCTRL, 0x69);
Data |= 0x03;
/*===================================================================
Function : InitDDR2CHC()
-Precondition :
-Input :
+Precondition :
+Input :
DramAttr: pointer point to DRAM_SYS_ATTR which consist the DDR and Dimm information
in MotherBoard
Output : Void
Purpose : Initialize DDR2 of CHC by standard sequence
-Reference :
+Reference :
===================================================================*/
// DDR2 CL=2 CL=3 CL=4 CL=5 (Burst type=interleave)(WR fine tune in code)
static const u16 CHC_MRS_table[4] = { 0x22B, 0x23B, 0x24B, 0x25B }; // Use 1X-bandwidth MA table to init DRAM
Status = VerifyChc();
if (Status != CB_SUCCESS)
PRINT_DEBUG_MEM("Error!!!!CHC init error!\r");
- //step 31. exit the initialization mode
+ //step 31. exit the initialization mode
Data = pci_read_config8(MEMCTRL, 0xdb);
Data &= 0x9F;
pci_write_config8(MEMCTRL, 0xdb, Data);
projects / coreboot.git / blobdiff