* Apparently these registers govern some sort of bus master behavior.
*/
-static void northbridge_init(device_t dev)
+static void northbridge_init(device_t dev)
{
device_t fb_dev;
unsigned long fb;
pci_write_config8(dev, 0x84, 0x80);
pci_write_config16(dev, 0x80, 0x610f);
pci_write_config32(dev, 0x88, 0x00000002);
-
+
fb_dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x3122, 0);
if (fb_dev) {
/* Fixup GART and framebuffer addresses properly.
}
}
-static void nullfunc(void)
+static void nullfunc(device_t dev)
{
/* Nothing to do */
}
.device = PCI_DEVICE_ID_VIA_8633_1,
};
-static void vga_init(device_t dev)
-{
- //unsigned long fb;
- //msr_t clocks1,clocks2,instructions,setup;
-
- printk(BIOS_DEBUG, "VGA random fixup ...\n");
- pci_write_config8(dev, 0x04, 0x07);
- pci_write_config8(dev, 0x0d, 0x20);
- pci_write_config32(dev,0x10,0xd8000008);
- pci_write_config32(dev,0x14,0xdc000000);
-
- // set up performnce counters for debugging vga init sequence
- //setup.lo = 0x1c0; // count instructions
- //wrmsr(0x187,setup);
- //instructions.hi = 0;
- //instructions.lo = 0;
- //wrmsr(0xc2,instructions);
- //clocks1 = rdmsr(0x10);
-
-
-#if 0
- /* code to make vga init go through the emulator - as of yet this does not workfor the epia-m */
- pci_dev_init(dev);
-
- call_bios_interrupt(0x10,0x4f1f,0x8003,1,0);
-
- //clocks2 = rdmsr(0x10);
- //instructions = rdmsr(0xc2);
-
- printk(BIOS_DEBUG, "Clocks 1 = %08x:%08x\n",clocks1.hi,clocks1.lo);
- printk(BIOS_DEBUG, "Clocks 2 = %08x:%08x\n",clocks2.hi,clocks2.lo);
- printk(BIOS_DEBUG, "Instructions = %08x:%08x\n",instructions.hi,instructions.lo);
-
-#else
-
- /* code to make vga init run in real mode - does work but against the current coreboot philosophy */
- printk(BIOS_DEBUG, "INSTALL REAL-MODE IDT\n");
- setup_realmode_idt();
- printk(BIOS_DEBUG, "DO THE VGA BIOS\n");
- do_vgabios();
-
- //clocks2 = rdmsr(0x10);
- //instructions = rdmsr(0xc2);
-
- //printk(BIOS_DEBUG, "Clocks 1 = %08x:%08x\n",clocks1.hi,clocks1.lo);
- //printk(BIOS_DEBUG, "Clocks 2 = %08x:%08x\n",clocks2.hi,clocks2.lo);
- //printk(BIOS_DEBUG, "Instructions = %08x:%08x\n",instructions.hi,instructions.lo);
-
- vga_enable_console();
-
-#endif
-
- pci_write_config32(dev,0x30,0);
-
- /* Set the vga mtrrs - disable for the moment as the add_var_mtrr function has vapourised */
-#if 0
- add_var_mtrr( 0xd0000000 >> 10, 0x08000000>>10, MTRR_TYPE_WRCOMB);
- fb = pci_read_config32(dev,0x10); // get the fb address
- add_var_mtrr( fb>>10, 8192, MTRR_TYPE_WRCOMB);
-#endif
-}
-
-static struct device_operations vga_operations = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = vga_init,
- .ops_pci = 0,
-};
-
-static const struct pci_driver vga_driver __pci_driver = {
- .ops = &vga_operations,
- .vendor = PCI_VENDOR_ID_VIA,
- .device = 0x3122,
-};
-
-static void ram_resource(device_t dev, unsigned long index,
- unsigned long basek, unsigned long sizek)
-{
- struct resource *resource;
-
- if (!sizek) {
- return;
- }
- resource = new_resource(dev, index);
- resource->base = ((resource_t)basek) << 10;
- resource->size = ((resource_t)sizek) << 10;
- resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
- IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
-}
-
-static void tolm_test(void *gp, struct device *dev, struct resource *new)
-{
- struct resource **best_p = gp;
- struct resource *best;
- best = *best_p;
- if (!best || (best->base > new->base)) {
- best = new;
- }
- *best_p = best;
-}
-
-static uint32_t find_pci_tolm(struct bus *bus)
-{
- struct resource *min;
- uint32_t tolm;
- min = 0;
- search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
- tolm = 0xffffffffUL;
- if (min && tolm > min->base) {
- tolm = min->base;
- }
- return tolm;
-}
-
#if CONFIG_WRITE_HIGH_TABLES==1
/* maximum size of high tables in KB */
#define HIGH_TABLES_SIZE 64
printk(BIOS_SPEW, "Entering vt8623 pci_domain_set_resources.\n");
- pci_tolm = find_pci_tolm(&dev->link[0]);
- mc_dev = dev->link[0].children;
+ pci_tolm = find_pci_tolm(dev->link_list);
+ mc_dev = dev->link_list->children;
if (mc_dev) {
unsigned long tomk, tolmk;
unsigned char rambits;
for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
unsigned char reg;
reg = pci_read_config8(mc_dev, ramregs[i]);
- /* these are ENDING addresses, not sizes.
+ /* these are ENDING addresses, not sizes.
* if there is memory in this slot, then reg will be > rambits.
- * So we just take the max, that gives us total.
+ * So we just take the max, that gives us total.
* We take the highest one to cover for once and future coreboot
* bugs. We warn about bugs.
*/
if (reg > rambits)
rambits = reg;
if (reg < rambits)
- printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n",
+ printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n",
ramregs[i]);
}
printk(BIOS_DEBUG, "I would set ram size to 0x%x Kbytes\n", (rambits)*16*1024);
ram_resource(dev, idx++, 0, 640); /* first 640k */
ram_resource(dev, idx++, 768, tolmk - 768); /* leave a hole for vga */
}
- assign_resources(&dev->link[0]);
+ assign_resources(dev->link_list);
}
static struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources,
- .enable_resources = enable_childrens_resources,
- .init = 0,
+ .enable_resources = NULL,
+ .init = NULL,
.scan_bus = pci_domain_scan_bus,
-};
+};
static void cpu_bus_init(device_t dev)
{
- initialize_cpus(&dev->link[0]);
+ initialize_cpus(dev->link_list);
}
static void cpu_bus_noop(device_t dev)
projects / coreboot.git / blobdiff