#include <console/console.h>
#include <arch/io.h>
#include <stdint.h>
-#include <mem.h>
-#include <part/sizeram.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ids.h>
#include <device/hypertransport.h>
-#include <device/chip.h>
+#include <cpu/cpu.h>
#include <stdlib.h>
#include <string.h>
#include <bitops.h>
#include "chip.h"
#include "northbridge.h"
-struct mem_range *sizeram(void)
+/*
+ * This fixup is based on capturing values from an Award bios. Without
+ * this fixup the DMA write performance is awful (i.e. hdparm -t /dev/hda is 20x
+ * slower than normal, ethernet drops packets).
+ * Apparently these registers govern some sort of bus master behavior.
+ */
+static void northbridge_init(device_t dev)
{
- unsigned long mmio_basek;
- static struct mem_range mem[10];
- device_t dev;
- int i, idx;
+ printk(BIOS_SPEW, "VT8601 random fixup ...\n");
+ pci_write_config8(dev, 0x70, 0xc0);
+ pci_write_config8(dev, 0x71, 0x88);
+ pci_write_config8(dev, 0x72, 0xec);
+ pci_write_config8(dev, 0x73, 0x0c);
+ pci_write_config8(dev, 0x74, 0x0e);
+ pci_write_config8(dev, 0x75, 0x81);
+ pci_write_config8(dev, 0x76, 0x52);
+}
-#warning "FIXME handle interleaved nodes"
- dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
- if (!dev) {
- printk_err("Cannot find PCI: 0:18.1\n");
- return 0;
- }
- mmio_basek = (dev_root.resource[1].base >> 10);
- /* Round mmio_basek to something the processor can support */
- mmio_basek &= ~((1 << 6) -1);
+static struct device_operations northbridge_operations = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = northbridge_init,
+ .enable = 0,
+ .ops_pci = 0,
+};
-#if 1
-#warning "FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M MMIO hole"
- /* Round the mmio hold to 256M */
- mmio_basek &= ~((256*1024) - 1);
-#endif
+static const struct pci_driver northbridge_driver __pci_driver = {
+ .ops = &northbridge_operations,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = 0x0601, /* 0x8601 is the AGP bridge? */
+};
-#if 1
- printk_debug("mmio_base: %dKB\n", mmio_basek);
+#if CONFIG_WRITE_HIGH_TABLES==1
+/* maximum size of high tables in KB */
+#define HIGH_TABLES_SIZE 64
+extern uint64_t high_tables_base, high_tables_size;
#endif
- for(idx = i = 0; i < 8; i++) {
- uint32_t base, limit;
- unsigned basek, limitk, sizek;
- base = pci_read_config32(dev, 0x40 + (i<<3));
- limit = pci_read_config32(dev, 0x44 + (i<<3));
- if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
- continue;
- }
- basek = (base & 0xffff0000) >> 2;
- limitk = ((limit + 0x00010000) & 0xffff0000) >> 2;
- sizek = limitk - basek;
- if ((idx > 0) &&
- ((mem[idx -1].basek + mem[idx - 1].sizek) == basek)) {
- mem[idx -1].sizek += sizek;
- }
- else {
- mem[idx].basek = basek;
- mem[idx].sizek = sizek;
- idx++;
+static void pci_domain_set_resources(device_t dev)
+{
+ static const uint8_t ramregs[] = {
+ 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x56, 0x57
+ };
+ device_t mc_dev;
+ uint32_t pci_tolm;
+
+ pci_tolm = find_pci_tolm(dev->link_list);
+ mc_dev = dev->link_list->children;
+ if (mc_dev) {
+ unsigned long tomk, tolmk;
+ unsigned char rambits;
+ int i, idx;
+
+ for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
+ unsigned char reg;
+ reg = pci_read_config8(mc_dev, ramregs[i]);
+ /* these are ENDING addresses, not sizes.
+ * if there is memory in this slot, then reg will be > rambits.
+ * So we just take the max, that gives us total.
+ * We take the highest one to cover for once and future coreboot
+ * bugs. We warn about bugs.
+ */
+ if (reg > rambits)
+ rambits = reg;
+ if (reg < rambits)
+ printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n",
+ ramregs[i]);
}
- /* See if I need to split the region to accomodate pci memory space */
- if ((mem[idx - 1].basek <= mmio_basek) &&
- ((mem[idx - 1].basek + mem[idx - 1].sizek) > mmio_basek)) {
- if (mem[idx - 1].basek < mmio_basek) {
- unsigned pre_sizek;
- pre_sizek = mmio_basek - mem[idx - 1].basek;
- mem[idx].basek = mmio_basek;
- mem[idx].sizek = mem[idx - 1].sizek - pre_sizek;
- mem[idx - 1].sizek = pre_sizek;
- idx++;
- }
- if ((mem[idx - 1].basek + mem[idx - 1].sizek) <= 4*1024*1024) {
- idx -= 1;
- }
- else {
- mem[idx - 1].basek = 4*1024*1024;
- mem[idx - 1].sizek -= (4*1024*1024 - mmio_basek);
- }
+ printk(BIOS_DEBUG, "I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024);
+ tomk = rambits*8*1024;
+ /* Compute the top of Low memory */
+ tolmk = pci_tolm >> 10;
+ if (tolmk >= tomk) {
+ /* The PCI hole does does not overlap the memory.
+ */
+ tolmk = tomk;
}
- }
-#if 0
- for(i = 0; i < idx; i++) {
- printk_debug("mem[%d].basek = %08x mem[%d].sizek = %08x\n",
- i, mem[i].basek, i, mem[i].sizek);
- }
+
+#if CONFIG_WRITE_HIGH_TABLES == 1
+ high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024;
+ high_tables_size = HIGH_TABLES_SIZE* 1024;
+ printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size);
#endif
- while(idx < sizeof(mem)/sizeof(mem[0])) {
- mem[idx].basek = 0;
- mem[idx].sizek = 0;
- idx++;
+
+ /* Report the memory regions */
+ idx = 10;
+ ram_resource(dev, idx++, 0, tolmk);
}
- return mem;
+ assign_resources(dev->link_list);
+}
+
+static struct device_operations pci_domain_ops = {
+ .read_resources = pci_domain_read_resources,
+ .set_resources = pci_domain_set_resources,
+ .enable_resources = NULL,
+ .init = NULL,
+ .scan_bus = pci_domain_scan_bus,
+};
+
+static void cpu_bus_init(device_t dev)
+{
+ initialize_cpus(dev->link_list);
}
-static void enumerate(struct chip *chip)
+
+static void cpu_bus_noop(device_t dev)
+{
+}
+
+static struct device_operations cpu_bus_ops = {
+ .read_resources = cpu_bus_noop,
+ .set_resources = cpu_bus_noop,
+ .enable_resources = cpu_bus_noop,
+ .init = cpu_bus_init,
+ .scan_bus = 0,
+};
+
+static void enable_dev(struct device *dev)
{
- extern struct device_operations default_pci_ops_bus;
- chip_enumerate(chip);
- chip->dev->ops = &default_pci_ops_bus;
+ /* Set the operations if it is a special bus type */
+ if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
+ dev->ops = &pci_domain_ops;
+ pci_set_method(dev);
+ }
+ else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
+ dev->ops = &cpu_bus_ops;
+ }
}
-struct chip_control northbridge_via_vt8601_control = {
- .enumerate = enumerate,
- .name = "VIA vt8601 Northbridge",
+struct chip_operations northbridge_via_vt8601_ops = {
+ CHIP_NAME("VIA VT8601 Northbridge")
+ .enable_dev = enable_dev,
};
projects / coreboot.git / blobdiff