printk_foo -> printk(BIOS_FOO, ...)

[coreboot.git] / src / northbridge / via / vt8601 / northbridge.c

diff --git a/src/northbridge/via/vt8601/northbridge.c b/src/northbridge/via/vt8601/northbridge.c
index cf8e82907ccefbcbb9be136df3ef517a2ae79d3f..5af7836a9371903bb9300a3bd8ebe87613fdb778 100644 (file)
--- a/src/northbridge/via/vt8601/northbridge.c
+++ b/src/northbridge/via/vt8601/northbridge.c
@@ -5,6 +5,7 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/hypertransport.h>
+#include <cpu/cpu.h>
 #include <stdlib.h>
 #include <string.h>
 #include <bitops.h>
@@ -19,7 +20,7 @@
  */
 static void northbridge_init(device_t dev) 
 {
-       printk_spew("VT8601 random fixup ...\n");
+       printk(BIOS_SPEW, "VT8601 random fixup ...\n");
        pci_write_config8(dev, 0x70, 0xc0);
        pci_write_config8(dev, 0x71, 0x88);
        pci_write_config8(dev, 0x72, 0xec);
@@ -38,29 +39,12 @@ static struct device_operations northbridge_operations = {
        .ops_pci          = 0,
 };
 
-static struct pci_driver northbridge_driver __pci_driver = {
+static const struct pci_driver northbridge_driver __pci_driver = {
        .ops = &northbridge_operations,
        .vendor = PCI_VENDOR_ID_VIA,
        .device = 0x0601, /* 0x8601 is the AGP bridge? */
 };
 
-#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
-
-static void pci_domain_read_resources(device_t dev)
-{
-        struct resource *resource;
-
-        /* Initialize the system wide io space constraints */
-        resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
-        resource->limit = 0xffffUL;
-        resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-
-        /* Initialize the system wide memory resources constraints */
-        resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
-        resource->limit = 0xffffffffULL;
-        resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-}
-
 static void ram_resource(device_t dev, unsigned long index,
         unsigned long basek, unsigned long sizek)
 {
@@ -100,6 +84,12 @@ static uint32_t find_pci_tolm(struct bus *bus)
        return tolm;
 }
 
+#if CONFIG_WRITE_HIGH_TABLES==1
+/* maximum size of high tables in KB */
+#define HIGH_TABLES_SIZE 64
+extern uint64_t high_tables_base, high_tables_size;
+#endif
+
 static void pci_domain_set_resources(device_t dev)
 {
        static const uint8_t ramregs[] = {
@@ -115,22 +105,22 @@ static void pci_domain_set_resources(device_t dev)
                unsigned char rambits;
                int i, idx;
 
-               for(rambits = 0, i = 0; i < sizeof(ramregs)/sizeof(ramregs[0]); i++) {
+               for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
                        unsigned char reg;
                        reg = pci_read_config8(mc_dev, ramregs[i]);
                        /* these are ENDING addresses, not sizes. 
                         * if there is memory in this slot, then reg will be > rambits.
                         * So we just take the max, that gives us total. 
-                        * We take the highest one to cover for once and future linuxbios
+                        * We take the highest one to cover for once and future coreboot
                         * bugs. We warn about bugs.
                         */
                        if (reg > rambits)
                                rambits = reg;
                        if (reg < rambits)
-                               printk_err("ERROR! register 0x%x is not set!\n", 
+                               printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n", 
                                        ramregs[i]);
                }
-               printk_debug("I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024);
+               printk(BIOS_DEBUG, "I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024);
                tomk = rambits*8*1024;
                /* Compute the top of Low memory */
                tolmk = pci_tolm >> 10;
@@ -139,6 +129,13 @@ static void pci_domain_set_resources(device_t dev)
                         */
                        tolmk = tomk;
                }
+
+#if CONFIG_WRITE_HIGH_TABLES == 1
+               high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024;
+               high_tables_size = HIGH_TABLES_SIZE* 1024;
+               printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size);
+#endif
+
                /* Report the memory regions */
                idx = 10;
                ram_resource(dev, idx++, 0, tolmk);
@@ -146,12 +143,6 @@ static void pci_domain_set_resources(device_t dev)
        assign_resources(&dev->link[0]);
 }
 
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
-{
-        max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
-        return max;
-}
-
 static struct device_operations pci_domain_ops = {
         .read_resources   = pci_domain_read_resources,
         .set_resources    = pci_domain_set_resources,
@@ -190,6 +181,6 @@ static void enable_dev(struct device *dev)
 }
 
 struct chip_operations northbridge_via_vt8601_ops = {
-       CHIP_NAME("VIA vt8601 Northbridge")
+       CHIP_NAME("VIA VT8601 Northbridge")
        .enable_dev = enable_dev, 
 };