Same conversion as with resources from static arrays to lists, except

[coreboot.git] / src / northbridge / via / vt8601 / northbridge.c

diff --git a/src/northbridge/via/vt8601/northbridge.c b/src/northbridge/via/vt8601/northbridge.c
index 8fb82f0023a641998479c9f3cc6067c05a7698a7..1f15b7026ecc523ed130153d6b25523ca78dcf85 100644 (file)
--- a/src/northbridge/via/vt8601/northbridge.c
+++ b/src/northbridge/via/vt8601/northbridge.c
@@ -18,9 +18,9 @@
  * slower than normal, ethernet drops packets).
  * Apparently these registers govern some sort of bus master behavior.
  */
-static void northbridge_init(device_t dev) 
+static void northbridge_init(device_t dev)
 {
-       printk_spew("VT8601 random fixup ...\n");
+       printk(BIOS_SPEW, "VT8601 random fixup ...\n");
        pci_write_config8(dev, 0x70, 0xc0);
        pci_write_config8(dev, 0x71, 0x88);
        pci_write_config8(dev, 0x72, 0xec);
@@ -84,7 +84,7 @@ static uint32_t find_pci_tolm(struct bus *bus)
        return tolm;
 }
 
-#if CONFIG_HAVE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES==1
 /* maximum size of high tables in KB */
 #define HIGH_TABLES_SIZE 64
 extern uint64_t high_tables_base, high_tables_size;
@@ -98,8 +98,8 @@ static void pci_domain_set_resources(device_t dev)
        device_t mc_dev;
         uint32_t pci_tolm;
 
-        pci_tolm = find_pci_tolm(&dev->link[0]);
-       mc_dev = dev->link[0].children;
+        pci_tolm = find_pci_tolm(dev->link_list);
+       mc_dev = dev->link_list->children;
        if (mc_dev) {
                unsigned long tomk, tolmk;
                unsigned char rambits;
@@ -108,19 +108,19 @@ static void pci_domain_set_resources(device_t dev)
                for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
                        unsigned char reg;
                        reg = pci_read_config8(mc_dev, ramregs[i]);
-                       /* these are ENDING addresses, not sizes. 
+                       /* these are ENDING addresses, not sizes.
                         * if there is memory in this slot, then reg will be > rambits.
-                        * So we just take the max, that gives us total. 
+                        * So we just take the max, that gives us total.
                         * We take the highest one to cover for once and future coreboot
                         * bugs. We warn about bugs.
                         */
                        if (reg > rambits)
                                rambits = reg;
                        if (reg < rambits)
-                               printk_err("ERROR! register 0x%x is not set!\n", 
+                               printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n",
                                        ramregs[i]);
                }
-               printk_debug("I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024);
+               printk(BIOS_DEBUG, "I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024);
                tomk = rambits*8*1024;
                /* Compute the top of Low memory */
                tolmk = pci_tolm >> 10;
@@ -130,17 +130,17 @@ static void pci_domain_set_resources(device_t dev)
                        tolmk = tomk;
                }
 
-#if CONFIG_HAVE_HIGH_TABLES == 1
+#if CONFIG_WRITE_HIGH_TABLES == 1
                high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024;
                high_tables_size = HIGH_TABLES_SIZE* 1024;
-               printk_debug("tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size);
+               printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size);
 #endif
 
                /* Report the memory regions */
                idx = 10;
                ram_resource(dev, idx++, 0, tolmk);
        }
-       assign_resources(&dev->link[0]);
+       assign_resources(dev->link_list);
 }
 
 static struct device_operations pci_domain_ops = {
@@ -149,11 +149,11 @@ static struct device_operations pci_domain_ops = {
         .enable_resources = enable_childrens_resources,
         .init             = 0,
         .scan_bus         = pci_domain_scan_bus,
-};  
+};
 
 static void cpu_bus_init(device_t dev)
 {
-        initialize_cpus(&dev->link[0]);
+        initialize_cpus(dev->link_list);
 }
 
 static void cpu_bus_noop(device_t dev)
@@ -182,5 +182,5 @@ static void enable_dev(struct device *dev)
 
 struct chip_operations northbridge_via_vt8601_ops = {
        CHIP_NAME("VIA VT8601 Northbridge")
-       .enable_dev = enable_dev, 
+       .enable_dev = enable_dev,
 };