Since some people disapprove of white space cleanups mixed in regular commits

[coreboot.git] / src / northbridge / via / cn700 / raminit.c

diff --git a/src/northbridge/via/cn700/raminit.c b/src/northbridge/via/cn700/raminit.c
index 715305268ec92be72815afe6489fa7f9da9ab9cd..20b0afeb6ecc0d5a546ee82b00649ddf68c51984 100644 (file)
--- a/src/northbridge/via/cn700/raminit.c
+++ b/src/northbridge/via/cn700/raminit.c
@@ -21,13 +21,10 @@
  */
 
 #include <spd.h>
-#include <sdram_mode.h>
 #include <delay.h>
 #include "cn700.h"
 
-// #define DEBUG_RAM_SETUP 1
-
-#ifdef DEBUG_RAM_SETUP
+#ifdef CONFIG_DEBUG_RAM_SETUP
 #define PRINT_DEBUG_MEM(x)             print_debug(x)
 #define PRINT_DEBUG_MEM_HEX8(x)                print_debug_hex8(x)
 #define PRINT_DEBUG_MEM_HEX16(x)       print_debug_hex16(x)
@@ -51,16 +48,10 @@ static void do_ram_command(device_t dev, u8 command)
        reg &= 0xf8;            /* Clear bits 2-0. */
        reg |= command;
        pci_write_config8(dev, DRAM_MISC_CTL, reg);
-
-       PRINT_DEBUG_MEM("    Sending RAM command 0x");
-       PRINT_DEBUG_MEM_HEX8(reg);
-       PRINT_DEBUG_MEM(" to 0x");
-       PRINT_DEBUG_MEM_HEX32(0 + addr_offset);
-       PRINT_DEBUG_MEM("\r\n");
 }
 
 /**
- * Configure the bus between the CPU and the northbridge. This might be able to 
+ * Configure the bus between the CPU and the northbridge. This might be able to
  * be moved to post-ram code in the future. For the most part, these registers
  * should not be messed around with. These are too complex to explain short of
  * copying the datasheets into the comments, but most of these values are from
@@ -191,7 +182,7 @@ static void sdram_set_size(const struct mem_controller *ctrl)
        }
 
        if (result == 0xff)
-               die("DRAM module size too big, not supported by CN700\r\n");
+               die("DRAM module size too big, not supported by CN700\n");
 
        pci_write_config8(ctrl->d0f3, 0x40, result);
        pci_write_config8(ctrl->d0f3, 0x48, 0x00);
@@ -253,7 +244,7 @@ static void sdram_set_size(const struct mem_controller *ctrl)
 }
 
 /**
- * Set up various RAM and other control registers statically. Some of these may 
+ * Set up various RAM and other control registers statically. Some of these may
  * not be needed, other should be done with SPD info, but that's a project for
  * the future.
  */
@@ -397,30 +388,30 @@ static void sdram_enable(device_t dev, unsigned long rank_address)
        u8 i;
 
        /* 1. Apply NOP. */
-       PRINT_DEBUG_MEM("RAM Enable 1: Apply NOP\r\n");
+       PRINT_DEBUG_MEM("RAM Enable 1: Apply NOP\n");
        do_ram_command(dev, RAM_COMMAND_NOP);
        udelay(100);
        read32(rank_address + 0x10);
 
        /* 2. Precharge all. */
        udelay(400);
-       PRINT_DEBUG_MEM("RAM Enable 2: Precharge all\r\n");
+       PRINT_DEBUG_MEM("RAM Enable 2: Precharge all\n");
        do_ram_command(dev, RAM_COMMAND_PRECHARGE);
        read32(rank_address + 0x10);
 
        /* 3. Mode register set. */
-       PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\r\n");
+       PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\n");
        do_ram_command(dev, RAM_COMMAND_MRS);
        read32(rank_address + 0x120000);        /* EMRS DLL Enable */
        read32(rank_address + 0x800);           /* MRS DLL Reset */
 
        /* 4. Precharge all again. */
-       PRINT_DEBUG_MEM("RAM Enable 2: Precharge all\r\n");
+       PRINT_DEBUG_MEM("RAM Enable 2: Precharge all\n");
        do_ram_command(dev, RAM_COMMAND_PRECHARGE);
        read32(rank_address + 0x0);
 
        /* 5. Perform 8 refresh cycles. Wait tRC each time. */
-       PRINT_DEBUG_MEM("RAM Enable 3: CBR\r\n");
+       PRINT_DEBUG_MEM("RAM Enable 3: CBR\n");
        do_ram_command(dev, RAM_COMMAND_CBR);
        for (i = 0; i < 8; i++) {
                read32(rank_address + 0x20);
@@ -428,10 +419,10 @@ static void sdram_enable(device_t dev, unsigned long rank_address)
        }
 
        /* 6. Mode register set. */
-       PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\r\n");
+       PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\n");
        /* Safe value for now, BL=8, WR=5, CAS=4 */
        /*
-        * (E)MRS values are from the BPG. No direct explanation is given, but 
+        * (E)MRS values are from the BPG. No direct explanation is given, but
         * they should somehow conform to the JEDEC DDR2 SDRAM Specification
         * (JESD79-2C).
         */
@@ -441,7 +432,7 @@ static void sdram_enable(device_t dev, unsigned long rank_address)
        read32(rank_address + 0x120020); /* EMRS OCD Calibration Mode Exit */
 
        /* 8. Normal operation */
-       PRINT_DEBUG_MEM("RAM Enable 5: Normal operation\r\n");
+       PRINT_DEBUG_MEM("RAM Enable 5: Normal operation\n");
        do_ram_command(dev, RAM_COMMAND_NORMAL);
        read32(rank_address + 0x30);
 }