* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#include <console/console.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
+#include <pc80/mc146818rtc.h>
#include <spd.h>
+#include <string.h>
+#include <arch/romcc_io.h>
#include "raminit.h"
#include "i945.h"
#define RAM_EMRS_2 (0x1 << 21)
#define RAM_EMRS_3 (0x2 << 21)
-static void do_ram_command(u32 command)
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+ return smbus_read_byte(device, address);
+}
+
+static __attribute__((noinline)) void do_ram_command(u32 command)
{
u32 reg32;
MCHBAR32(DCC) = reg32; /* This is the actual magic */
PRINTK_DEBUG("...done\n");
+
+ udelay(1);
}
static void ram_read32(u32 offset)
static int memclk(void)
{
int offset = 0;
-#ifdef CHIPSET_I945GM
+#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
offset++;
#endif
switch (((MCHBAR32(CLKCFG) >> 4) & 7) - offset) {
return -1;
}
-#ifdef CHIPSET_I945GM
-static int fsbclk(void)
+#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
+static u16 fsbclk(void)
{
switch (MCHBAR32(CLKCFG) & 7) {
case 0: return 400;
case 3: return 667;
default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
}
- return -1;
+ return 0xffff;
}
-#endif
-#ifdef CHIPSET_I945GC
-static int fsbclk(void)
+#elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC)
+static u16 fsbclk(void)
{
switch (MCHBAR32(CLKCFG) & 7) {
case 0: return 1066;
case 2: return 800;
default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
}
- return -1;
+ return 0xffff;
}
#endif
{
u32 reg32;
-#ifdef MAXIMUM_SUPPORTED_FREQUENCY
- return MAXIMUM_SUPPORTED_FREQUENCY;
+#if CONFIG_MAXIMUM_SUPPORTED_FREQUENCY
+ return CONFIG_MAXIMUM_SUPPORTED_FREQUENCY;
#endif
- reg32 = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xe4);
+ reg32 = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xe4); /* CAPID0 + 4 */
reg32 &= (7 << 0);
switch (reg32) {
{
u32 reg32;
- reg32 = pci_read_config8(PCI_DEV(0, 0x00,0), 0xe4);
+ reg32 = pci_read_config32(PCI_DEV(0, 0x00,0), 0xe4); /* CAPID0 + 4 */
reg32 >>= 25;
reg32 &= 1;
{
u32 reg32;
- reg32 = pci_read_config8(PCI_DEV(0, 0x00,0), 0xe4);
+ reg32 = pci_read_config32(PCI_DEV(0, 0x00,0), 0xe4); /* CAPID0 + 4 */
reg32 >>= 24;
reg32 &= 1;
return (reg8 != 0);
}
-// TODO check if we ever need this function
+// TODO check if we ever need this function
#if 0
static int sdram_capabilities_MEM4G_disable(void)
{
u8 reg8;
- reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe5);
+ reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe5); /* CAPID0 + 5 */
reg8 &= (1 << 0);
return (reg8 != 0);
return (reg8);
}
-static void sdram_detect_errors(void)
+static void sdram_detect_errors(struct sys_info *sysinfo)
{
u8 reg8;
u8 do_reset = 0;
reg8 |= (1<<7);
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
+ /* clear self refresh if not wake-up from suspend */
+ if (sysinfo->boot_path != 2) {
+ MCHBAR8(0xf14) |= 3;
+ } else {
+ /* Validate self refresh config */
+ if (((sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED) ||
+ (sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED)) &&
+ !(MCHBAR8(0xf14) & (1<<0))) {
+ do_reset = 1;
+ }
+ if (((sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED) ||
+ (sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)) &&
+ !(MCHBAR8(0xf14) & (1<<1))) {
+ do_reset = 1;
+ }
+ }
+
+ if (do_reset) {
+ printk(BIOS_DEBUG, "Reset required.\n");
+ outb(0x00, 0xcf9);
+ outb(0x0e, 0xcf9);
+ for (;;) asm("hlt"); /* Wait for reset! */
+ }
}
/**
/**
* i945 supports two DIMMs, in two configurations:
*
- * - single channel with two dimms
- * - dual channel with one dimm per channel
+ * - single channel with two DIMMs
+ * - dual channel with one DIMM per channel
*
- * In practice dual channel mainboards have their spd at 0x50, 0x52
- * whereas single channel configurations have their spd at 0x50/x51
+ * In practice dual channel mainboards have their SPD at 0x50/0x52
+ * whereas single channel configurations have their SPD at 0x50/0x51.
*
* The capability register knows a lot about the channel configuration
- * but for now we stick with the information we gather from the SPD
- * ROMs
+ * but for now we stick with the information we gather via SPD.
*/
if (sdram_capabilities_dual_channel()) {
*/
for (i=0; i<(2 * DIMM_SOCKETS); i++) {
- u8 reg8, device = DIMM_SPD_BASE + i;
+ u8 reg8, device = DIMM0 + i;
/* Initialize the socket information with a sane value */
sysinfo->dimm[i] = SYSINFO_DIMM_NOT_POPULATED;
continue;
/* Is the current DIMM a stacked DIMM? */
- if (spd_read_byte(DIMM_SPD_BASE + i, SPD_NUM_DIMM_BANKS) & (1 << 4))
+ if (spd_read_byte(DIMM0 + i, SPD_NUM_DIMM_BANKS) & (1 << 4))
sysinfo->package = 1;
}
}
for (i=0; i<2*DIMM_SOCKETS; i++) {
if (sysinfo->dimm[i] != SYSINFO_DIMM_NOT_POPULATED)
- cas_mask &= spd_read_byte(DIMM_SPD_BASE + i, SPD_ACCEPTABLE_CAS_LATENCIES);
+ cas_mask &= spd_read_byte(DIMM0 + i, SPD_ACCEPTABLE_CAS_LATENCIES);
}
if(!cas_mask) {
continue;
}
- current_cas_mask = spd_read_byte(DIMM_SPD_BASE + i, SPD_ACCEPTABLE_CAS_LATENCIES);
+ current_cas_mask = spd_read_byte(DIMM0 + i, SPD_ACCEPTABLE_CAS_LATENCIES);
while (current_cas_mask) {
int highest_supported_cas = 0, current_cas = 0;
idx = highest_supported_cas - current_cas;
PRINTK_DEBUG("idx=%d, ", idx);
- PRINTK_DEBUG("tCLK=%x, ", spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[2*idx]));
- PRINTK_DEBUG("tAC=%x", spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[(2*idx)+1]));
+ PRINTK_DEBUG("tCLK=%x, ", spd_read_byte(DIMM0 + i, spd_lookup_table[2*idx]));
+ PRINTK_DEBUG("tAC=%x", spd_read_byte(DIMM0 + i, spd_lookup_table[(2*idx)+1]));
- if (spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[2*idx]) <= ddr2_speeds_table[2*j] &&
- spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[(2*idx)+1]) <= ddr2_speeds_table[(2*j)+1]) {
+ if (spd_read_byte(DIMM0 + i, spd_lookup_table[2*idx]) <= ddr2_speeds_table[2*j] &&
+ spd_read_byte(DIMM0 + i, spd_lookup_table[(2*idx)+1]) <= ddr2_speeds_table[(2*j)+1]) {
PRINTK_DEBUG(": OK\n");
break;
}
if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
continue;
- reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
+ reg8 = spd_read_byte(DIMM0 + i, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
if (!reg8) {
die("Invalid tRAS value.\n");
}
if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
continue;
- reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_MIN_ROW_PRECHARGE_TIME);
+ reg8 = spd_read_byte(DIMM0 + i, SPD_MIN_ROW_PRECHARGE_TIME);
if (!reg8) {
die("Invalid tRP value.\n");
}
if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
continue;
- reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_MIN_RAS_TO_CAS_DELAY);
+ reg8 = spd_read_byte(DIMM0 + i, SPD_MIN_RAS_TO_CAS_DELAY);
if (!reg8) {
die("Invalid tRCD value.\n");
}
if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
continue;
- reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_WRITE_RECOVERY_TIME);
+ reg8 = spd_read_byte(DIMM0 + i, SPD_WRITE_RECOVERY_TIME);
if (!reg8) {
die("Invalid tWR value.\n");
}
if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
continue;
- refresh = spd_read_byte(DIMM_SPD_BASE + i, SPD_REFRESH) & ~(1 << 7);
+ refresh = spd_read_byte(DIMM0 + i, SPD_REFRESH) & ~(1 << 7);
/* 15.6us */
if (!refresh)
if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
continue;
- if (!(spd_read_byte(DIMM_SPD_BASE + i, SPD_SUPPORTED_BURST_LENGTHS) & SPD_BURST_LENGTH_8))
+ if (!(spd_read_byte(DIMM0 + i, SPD_SUPPORTED_BURST_LENGTHS) & SPD_BURST_LENGTH_8))
die("Only DDR-II RAM with burst length 8 is supported by this chipset.\n");
}
}
return nc;
}
-#ifdef CHIPSET_I945GM
+#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
/* Strength multiplier tables */
static const u8 dual_channel_strength_multiplier[] = {
0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
0x33, 0x00, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
0x33, 0x00, 0x11, 0x00, 0x44, 0x44, 0x33, 0x11
};
-#endif
-#ifdef CHIPSET_I945GC
+#elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC)
static const u8 dual_channel_strength_multiplier[] = {
0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
reg32 |= (1 << 6) | (1 << 4);
MCHBAR32(DRTST) = reg32;
- asm volatile ("nop; nop;");
+ asm volatile ("nop; nop;" ::: "memory");
reg32 = MCHBAR32(DRTST);
if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
continue;
- sz = sdram_get_dimm_size(DIMM_SPD_BASE + i);
+ sz = sdram_get_dimm_size(DIMM0 + i);
- sysinfo->banks[i] = spd_read_byte(DIMM_SPD_BASE + i, SPD_NUM_BANKS_PER_SDRAM); /* banks */
+ sysinfo->banks[i] = spd_read_byte(DIMM0 + i, SPD_NUM_BANKS_PER_SDRAM); /* banks */
if (sz.side1 < 30)
die("DDR-II rank size smaller than 128MB is not supported.\n");
continue;
}
- device = DIMM_SPD_BASE + i;
+ device = DIMM0 + i;
value = spd_read_byte(device, SPD_NUM_ROWS); /* rows */
columnsrows = (value & 0x0f);
printk(BIOS_DEBUG, "Single Channel 0 only.\n");
}
+ /* Now disable channel XORing */
reg32 |= (1 << 10);
MCHBAR32(DCC) = reg32;
MCHBAR32(PLLMON) = 0x80800000;
sysinfo->fsb_frequency = fsbclk();
- if (sysinfo->fsb_frequency == -1)
+ if (sysinfo->fsb_frequency == 0xffff)
die("Unsupported FSB speed");
/* Program CPCTL according to FSB speed */
if (voltage == VOLTAGE_1_05)
freq = CRCLK_250MHz;
else
- freq = CRCLK_400MHz;
+ freq = CRCLK_400MHz; /* 1.5V requires 400MHz */
break;
case GFX_FREQUENCY_CAP_250MHZ: freq = CRCLK_250MHz; break;
case GFX_FREQUENCY_CAP_200MHZ: freq = CRCLK_200MHz; break;
{
u32 clkcfg;
u8 reg8;
- u8 offset = 0;
-#ifdef CHIPSET_I945GM
- offset++;
-#endif
printk(BIOS_DEBUG, "Setting Memory Frequency... ");
}
switch (sysinfo->memory_frequency) {
- case 400: clkcfg |= ((1+offset) << 4); break;
- case 533: clkcfg |= ((2+offset) << 4); break;
- case 667: clkcfg |= ((3+offset) << 4); break;
+ case 400: clkcfg |= (2 << 4); break;
+ case 533: clkcfg |= (3 << 4); break;
+ case 667: clkcfg |= (4 << 4); break;
default: die("Target Memory Frequency Error");
}
clkcfg |= (1 << 10);
MCHBAR32(CLKCFG) = clkcfg;
- __asm__ __volatile__ (
+ asm volatile (
" movl $0x100, %%ecx\n"
"delay_update:\n"
" nop\n"
" loop delay_update\n"
: /* No outputs */
: /* No inputs */
- : "%ecx"
+ : "%ecx", "memory"
);
clkcfg &= ~(1 << 10);
/**
* We add the indices according to our clocks from CLKCFG.
*/
-#ifdef CHIPSET_I945GM
+#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
static const u32 data_clock_crossing[] = {
0x00100401, 0x00000000, /* DDR400 FSB400 */
0xffffffff, 0xffffffff, /* nonexistant */
0x08040120, 0x00000000, /* DDR400 FSB533 */
0x00100401, 0x00000000, /* DDR533 FSB533 */
- 0xffffffff, 0xffffffff, /* nonexistant */
+ 0x00010402, 0x00000000, /* DDR667 FSB533 - fake values */
0x04020120, 0x00000010, /* DDR400 FSB667 */
0x10040280, 0x00000040, /* DDR533 FSB667 */
0xffffffff, 0xffffffff, /* nonexistant */
};
-#endif
-#ifdef CHIPSET_I945GC
+#elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC)
/* i945 G/P */
static const u32 data_clock_crossing[] = {
0xffffffff, 0xffffffff, /* nonexistant */
0x10080201, 0x00000000, /* DDR400 FSB533 */
0x00100401, 0x00000000, /* DDR533 FSB533 */
- 0xffffffff, 0xffffffff, /* nonexistant */
+ 0x00010402, 0x00000000, /* DDR667 FSB533 - fake values */
0xffffffff, 0xffffffff, /* nonexistant */
0xffffffff, 0xffffffff, /* nonexistant */
0x00010800, 0x00000402, /* DDR400 FSB533 */
0x01000400, 0x00000200, /* DDR533 FSB533 */
- 0xffffffff, 0xffffffff, /* nonexistant */
+ 0x00020904, 0x00000000, /* DDR667 FSB533 - fake values */
0xffffffff, 0xffffffff, /* nonexistant */
0xffffffff, 0xffffffff, /* nonexistant */
if (sysinfo->interleaved) {
reg32 = MCHBAR32(DCC);
-#if CHANNEL_XOR_RANDOMIZATION
+#if CONFIG_CHANNEL_XOR_RANDOMIZATION
reg32 &= ~(1 << 10);
reg32 |= (1 << 9);
#else
* 0x30/0x32.
*/
+ /* TODO This is not implemented yet. Volunteers? */
}
static void sdram_save_receive_enable(void)
values[3] |= (reg32 >> (24 - 4)) & 0xf0;
/* coreboot only uses bytes 0 - 127 for its CMOS values so far
- * so we grad bytes 128 - 131 to save the receive enable values
+ * so we grab bytes 128 - 131 to save the receive enable values
*/
for (i=0; i<4; i++)
{
u8 clocks[2] = { 0, 0 };
-#ifdef CHIPSET_I945GM
+#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
#define CLOCKS_WIDTH 2
-#endif
-#ifdef CHIPSET_I945GC
+#elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC)
#define CLOCKS_WIDTH 3
#endif
if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED)
if (sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)
clocks[1] |= ((1 << CLOCKS_WIDTH)-1) << CLOCKS_WIDTH;
-#ifdef OVERRIDE_CLOCK_DISABLE
+#if CONFIG_OVERRIDE_CLOCK_DISABLE
/* Usually system firmware turns off system memory clock signals
* to unused SO-DIMM slots to reduce EMI and power consumption.
* However, the Kontron 986LCD-M does not like unused clock
* signals to be disabled.
- * If other similar mainboard occur, it would make sense to make
- * this an entry in the sysinfo structure, and pre-initialize that
- * structure in the mainboard's romstage.c main() function.
- * For now an #ifdef will do.
*/
clocks[0] = 0xf; /* force all clock gate pairs to enable */
struct sys_info sysinfo;
u8 reg8, cas_mask;
- sdram_detect_errors();
-
printk(BIOS_DEBUG, "Setting up RAM controller.\n");
memset(&sysinfo, 0, sizeof(sysinfo));
/* Look at the type of DIMMs and verify all DIMMs are x8 or x16 width */
sdram_get_dram_configuration(&sysinfo);
+ /* If error, do cold boot */
+ sdram_detect_errors(&sysinfo);
+
/* Check whether we have stacked DIMMs */
sdram_verify_package_type(&sysinfo);
projects / coreboot.git / blobdiff