Some more DIMM0 related cleanups and deduplication.

[coreboot.git] / src / northbridge / intel / i945 / raminit.c

diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index 62cd193d04c83dce7c43c235a76e954982cecb91..77b9ade6c47f30f543f741b71efa792f002e492f 100644 (file)
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -17,10 +17,13 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+#include <console/console.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>
 #include <pc80/mc146818rtc.h>
 #include <spd.h>
+#include <string.h>
+#include <arch/romcc_io.h>
 #include "raminit.h"
 #include "i945.h"
 
@@ -45,6 +48,11 @@
 #define RAM_EMRS_2                     (0x1 << 21)
 #define RAM_EMRS_3                     (0x2 << 21)
 
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+       return smbus_read_byte(device, address);
+}
+
 static __attribute__((noinline)) void do_ram_command(u32 command)
 {
        u32 reg32;
@@ -103,7 +111,7 @@ static int memclk(void)
 }
 
 #if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
-static int fsbclk(void)
+static u16 fsbclk(void)
 {
        switch (MCHBAR32(CLKCFG) & 7) {
        case 0: return 400;
@@ -111,10 +119,10 @@ static int fsbclk(void)
        case 3: return 667;
        default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
        }
-       return -1;
+       return 0xffff;
 }
 #elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC)
-static int fsbclk(void)
+static u16 fsbclk(void)
 {
        switch (MCHBAR32(CLKCFG) & 7) {
        case 0: return 1066;
@@ -122,7 +130,7 @@ static int fsbclk(void)
        case 2: return 800;
        default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
        }
-       return -1;
+       return 0xffff;
 }
 #endif
 
@@ -315,15 +323,14 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo)
        /**
         * i945 supports two DIMMs, in two configurations:
         *
-        * - single channel with two dimms
-        * - dual channel with one dimm per channel
+        * - single channel with two DIMMs
+        * - dual channel with one DIMM per channel
         *
-        * In practice dual channel mainboards have their spd at 0x50, 0x52
-        * whereas single channel configurations have their spd at 0x50/x51
+        * In practice dual channel mainboards have their SPD at 0x50/0x52
+        * whereas single channel configurations have their SPD at 0x50/0x51.
         *
         * The capability register knows a lot about the channel configuration
-        * but for now we stick with the information we gather from the SPD
-        * ROMs
+        * but for now we stick with the information we gather via SPD.
         */
 
        if (sdram_capabilities_dual_channel()) {
@@ -354,7 +361,7 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo)
         */
 
        for (i=0; i<(2 * DIMM_SOCKETS); i++) {
-               u8 reg8, device = DIMM_SPD_BASE + i;
+               u8 reg8, device = DIMM0 + i;
 
                /* Initialize the socket information with a sane value */
                sysinfo->dimm[i] = SYSINFO_DIMM_NOT_POPULATED;
@@ -445,7 +452,7 @@ static void sdram_verify_package_type(struct sys_info * sysinfo)
                        continue;
 
                /* Is the current DIMM a stacked DIMM? */
-               if (spd_read_byte(DIMM_SPD_BASE + i, SPD_NUM_DIMM_BANKS) & (1 << 4))
+               if (spd_read_byte(DIMM0 + i, SPD_NUM_DIMM_BANKS) & (1 << 4))
                        sysinfo->package = 1;
        }
 }
@@ -462,7 +469,7 @@ static u8 sdram_possible_cas_latencies(struct sys_info * sysinfo)
 
        for (i=0; i<2*DIMM_SOCKETS; i++) {
                if (sysinfo->dimm[i] != SYSINFO_DIMM_NOT_POPULATED)
-                       cas_mask &= spd_read_byte(DIMM_SPD_BASE + i, SPD_ACCEPTABLE_CAS_LATENCIES);
+                       cas_mask &= spd_read_byte(DIMM0 + i, SPD_ACCEPTABLE_CAS_LATENCIES);
        }
 
        if(!cas_mask) {
@@ -523,7 +530,7 @@ static void sdram_detect_cas_latency_and_ram_speed(struct sys_info * sysinfo, u8
                                continue;
                        }
 
-                       current_cas_mask = spd_read_byte(DIMM_SPD_BASE + i, SPD_ACCEPTABLE_CAS_LATENCIES);
+                       current_cas_mask = spd_read_byte(DIMM0 + i, SPD_ACCEPTABLE_CAS_LATENCIES);
 
                        while (current_cas_mask) {
                                int highest_supported_cas = 0, current_cas = 0;
@@ -545,11 +552,11 @@ static void sdram_detect_cas_latency_and_ram_speed(struct sys_info * sysinfo, u8
 
                                idx = highest_supported_cas - current_cas;
                                PRINTK_DEBUG("idx=%d, ", idx);
-                               PRINTK_DEBUG("tCLK=%x, ", spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[2*idx]));
-                               PRINTK_DEBUG("tAC=%x", spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[(2*idx)+1]));
+                               PRINTK_DEBUG("tCLK=%x, ", spd_read_byte(DIMM0 + i, spd_lookup_table[2*idx]));
+                               PRINTK_DEBUG("tAC=%x", spd_read_byte(DIMM0 + i, spd_lookup_table[(2*idx)+1]));
 
-                               if (spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[2*idx]) <= ddr2_speeds_table[2*j] &&
-                                               spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[(2*idx)+1]) <= ddr2_speeds_table[(2*j)+1]) {
+                               if (spd_read_byte(DIMM0 + i, spd_lookup_table[2*idx]) <= ddr2_speeds_table[2*j] &&
+                                               spd_read_byte(DIMM0 + i, spd_lookup_table[(2*idx)+1]) <= ddr2_speeds_table[(2*j)+1]) {
                                        PRINTK_DEBUG(":    OK\n");
                                        break;
                                }
@@ -613,7 +620,7 @@ static void sdram_detect_smallest_tRAS(struct sys_info * sysinfo)
                if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
                        continue;
 
-               reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
+               reg8 = spd_read_byte(DIMM0 + i, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
                if (!reg8) {
                        die("Invalid tRAS value.\n");
                }
@@ -653,7 +660,7 @@ static void sdram_detect_smallest_tRP(struct sys_info * sysinfo)
                if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
                        continue;
 
-               reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_MIN_ROW_PRECHARGE_TIME);
+               reg8 = spd_read_byte(DIMM0 + i, SPD_MIN_ROW_PRECHARGE_TIME);
                if (!reg8) {
                        die("Invalid tRP value.\n");
                }
@@ -694,7 +701,7 @@ static void sdram_detect_smallest_tRCD(struct sys_info * sysinfo)
                if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
                        continue;
 
-               reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_MIN_RAS_TO_CAS_DELAY);
+               reg8 = spd_read_byte(DIMM0 + i, SPD_MIN_RAS_TO_CAS_DELAY);
                if (!reg8) {
                        die("Invalid tRCD value.\n");
                }
@@ -734,7 +741,7 @@ static void sdram_detect_smallest_tWR(struct sys_info * sysinfo)
                if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
                        continue;
 
-               reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_WRITE_RECOVERY_TIME);
+               reg8 = spd_read_byte(DIMM0 + i, SPD_WRITE_RECOVERY_TIME);
                if (!reg8) {
                        die("Invalid tWR value.\n");
                }
@@ -815,7 +822,7 @@ static void sdram_detect_smallest_refresh(struct sys_info * sysinfo)
                if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
                        continue;
 
-               refresh = spd_read_byte(DIMM_SPD_BASE + i, SPD_REFRESH) & ~(1 << 7);
+               refresh = spd_read_byte(DIMM0 + i, SPD_REFRESH) & ~(1 << 7);
 
                /* 15.6us */
                if (!refresh)
@@ -843,7 +850,7 @@ static void sdram_verify_burst_length(struct sys_info * sysinfo)
                if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
                        continue;
 
-               if (!(spd_read_byte(DIMM_SPD_BASE + i, SPD_SUPPORTED_BURST_LENGTHS) & SPD_BURST_LENGTH_8))
+               if (!(spd_read_byte(DIMM0 + i, SPD_SUPPORTED_BURST_LENGTHS) & SPD_BURST_LENGTH_8))
                        die("Only DDR-II RAM with burst length 8 is supported by this chipset.\n");
        }
 }
@@ -1463,9 +1470,9 @@ static void sdram_detect_dimm_size(struct sys_info * sysinfo)
                if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
                        continue;
 
-               sz = sdram_get_dimm_size(DIMM_SPD_BASE + i);
+               sz = sdram_get_dimm_size(DIMM0 + i);
 
-               sysinfo->banks[i] = spd_read_byte(DIMM_SPD_BASE + i, SPD_NUM_BANKS_PER_SDRAM);  /* banks */
+               sysinfo->banks[i] = spd_read_byte(DIMM0 + i, SPD_NUM_BANKS_PER_SDRAM);  /* banks */
 
                if (sz.side1 < 30)
                        die("DDR-II rank size smaller than 128MB is not supported.\n");
@@ -1557,7 +1564,7 @@ static int sdram_set_row_attributes(struct sys_info *sysinfo)
                        continue;
                }
 
-               device = DIMM_SPD_BASE + i;
+               device = DIMM0 + i;
 
                value = spd_read_byte(device, SPD_NUM_ROWS);    /* rows */
                columnsrows = (value & 0x0f);
@@ -1929,7 +1936,7 @@ static void sdram_program_pll_settings(struct sys_info *sysinfo)
        MCHBAR32(PLLMON) = 0x80800000;
 
        sysinfo->fsb_frequency = fsbclk();
-       if (sysinfo->fsb_frequency == -1)
+       if (sysinfo->fsb_frequency == 0xffff)
                die("Unsupported FSB speed");
 
        /* Program CPCTL according to FSB speed */