Make i945/raminit.c:fsbclk() return u16 rather than int

[coreboot.git] / src / northbridge / intel / i945 / raminit.c

diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index 906c8f0dc1240d7f888defbdea17558c95f4e801..1595b8b3bc092ceb87f037aa1c6d2074270a7fab 100644 (file)
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -19,6 +19,7 @@
 
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>
+#include <pc80/mc146818rtc.h>
 #include <spd.h>
 #include "raminit.h"
 #include "i945.h"
@@ -44,7 +45,7 @@
 #define RAM_EMRS_2                     (0x1 << 21)
 #define RAM_EMRS_3                     (0x2 << 21)
 
-static void do_ram_command(u32 command)
+static __attribute__((noinline)) void do_ram_command(u32 command)
 {
        u32 reg32;
 
@@ -61,6 +62,8 @@ static void do_ram_command(u32 command)
        MCHBAR32(DCC) = reg32;  /* This is the actual magic */
 
        PRINTK_DEBUG("...done\n");
+
+       udelay(1);
 }
 
 static void ram_read32(u32 offset)
@@ -87,7 +90,7 @@ static void sdram_dump_mchbar_registers(void)
 static int memclk(void)
 {
        int offset = 0;
-#ifdef CHIPSET_I945GM
+#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
        offset++;
 #endif
        switch (((MCHBAR32(CLKCFG) >> 4) & 7) - offset) {
@@ -99,8 +102,8 @@ static int memclk(void)
        return -1;
 }
 
-#ifdef CHIPSET_I945GM
-static int fsbclk(void)
+#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
+static u16 fsbclk(void)
 {
        switch (MCHBAR32(CLKCFG) & 7) {
        case 0: return 400;
@@ -108,11 +111,10 @@ static int fsbclk(void)
        case 3: return 667;
        default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
        }
-       return -1;
+       return 0xffff;
 }
-#endif
-#ifdef CHIPSET_I945GC
-static int fsbclk(void)
+#elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC)
+static u16 fsbclk(void)
 {
        switch (MCHBAR32(CLKCFG) & 7) {
        case 0: return 1066;
@@ -120,7 +122,7 @@ static int fsbclk(void)
        case 2: return 800;
        default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
        }
-       return -1;
+       return 0xffff;
 }
 #endif
 
@@ -128,11 +130,11 @@ static int sdram_capabilities_max_supported_memory_frequency(void)
 {
        u32 reg32;
 
-#ifdef MAXIMUM_SUPPORTED_FREQUENCY
-       return MAXIMUM_SUPPORTED_FREQUENCY;
+#if CONFIG_MAXIMUM_SUPPORTED_FREQUENCY
+       return CONFIG_MAXIMUM_SUPPORTED_FREQUENCY;
 #endif
 
-       reg32 = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xe4);
+       reg32 = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xe4); /* CAPID0 + 4 */
        reg32 &= (7 << 0);
 
        switch (reg32) {
@@ -156,7 +158,7 @@ static int sdram_capabilities_interleave(void)
 {
        u32 reg32;
 
-       reg32 = pci_read_config8(PCI_DEV(0, 0x00,0), 0xe4);
+       reg32 = pci_read_config32(PCI_DEV(0, 0x00,0), 0xe4); /* CAPID0 + 4 */
        reg32 >>= 25;
        reg32 &= 1;
 
@@ -172,7 +174,7 @@ static int sdram_capabilities_dual_channel(void)
 {
        u32 reg32;
 
-       reg32 = pci_read_config8(PCI_DEV(0, 0x00,0), 0xe4);
+       reg32 = pci_read_config32(PCI_DEV(0, 0x00,0), 0xe4); /* CAPID0 + 4 */
        reg32 >>= 24;
        reg32 &= 1;
 
@@ -199,13 +201,13 @@ static int sdram_capabilities_two_dimms_per_channel(void)
        return (reg8 != 0);
 }
 
-// TODO check if we ever need this function 
+// TODO check if we ever need this function
 #if 0
 static int sdram_capabilities_MEM4G_disable(void)
 {
        u8 reg8;
 
-       reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe5);
+       reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe5); /* CAPID0 + 5 */
        reg8 &= (1 << 0);
 
        return (reg8 != 0);
@@ -228,7 +230,7 @@ static int sdram_capabilities_core_frequencies(void)
        return (reg8);
 }
 
-static void sdram_detect_errors(void)
+static void sdram_detect_errors(struct sys_info *sysinfo)
 {
        u8 reg8;
        u8 do_reset = 0;
@@ -269,6 +271,29 @@ static void sdram_detect_errors(void)
        reg8 |= (1<<7);
        pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
 
+       /* clear self refresh if not wake-up from suspend */
+       if (sysinfo->boot_path != 2) {
+               MCHBAR8(0xf14) |= 3;
+       } else {
+               /* Validate self refresh config */
+               if (((sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED) ||
+                    (sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED)) &&
+                   !(MCHBAR8(0xf14) & (1<<0))) {
+                       do_reset = 1;
+               }
+               if (((sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED) ||
+                    (sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)) &&
+                   !(MCHBAR8(0xf14) & (1<<1))) {
+                       do_reset = 1;
+               }
+       }
+
+       if (do_reset) {
+               printk(BIOS_DEBUG, "Reset required.\n");
+               outb(0x00, 0xcf9);
+               outb(0x0e, 0xcf9);
+               for (;;) asm("hlt"); /* Wait for reset! */
+       }
 }
 
 /**
@@ -1019,7 +1044,7 @@ static const u32 *slew_group_lookup(int dual_channel, int index)
        return nc;
 }
 
-#ifdef CHIPSET_I945GM
+#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
 /* Strength multiplier tables */
 static const u8 dual_channel_strength_multiplier[] = {
        0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
@@ -1074,8 +1099,7 @@ static const u8 single_channel_strength_multiplier[] = {
        0x33, 0x00, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
        0x33, 0x00, 0x11, 0x00, 0x44, 0x44, 0x33, 0x11
 };
-#endif
-#ifdef CHIPSET_I945GC
+#elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC)
 static const u8 dual_channel_strength_multiplier[] = {
        0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
        0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
@@ -1311,7 +1335,7 @@ static void sdram_enable_system_memory_io(struct sys_info *sysinfo)
        reg32 |= (1 << 6) | (1 << 4);
        MCHBAR32(DRTST) = reg32;
 
-       asm volatile ("nop; nop;");
+       asm volatile ("nop; nop;" ::: "memory");
 
        reg32 = MCHBAR32(DRTST);
 
@@ -1890,6 +1914,7 @@ static void sdram_set_channel_mode(struct sys_info *sysinfo)
                printk(BIOS_DEBUG, "Single Channel 0 only.\n");
        }
 
+       /* Now disable channel XORing */
        reg32 |= (1 << 10);
 
        MCHBAR32(DCC) = reg32;
@@ -1904,7 +1929,7 @@ static void sdram_program_pll_settings(struct sys_info *sysinfo)
        MCHBAR32(PLLMON) = 0x80800000;
 
        sysinfo->fsb_frequency = fsbclk();
-       if (sysinfo->fsb_frequency == -1)
+       if (sysinfo->fsb_frequency == 0xffff)
                die("Unsupported FSB speed");
 
        /* Program CPCTL according to FSB speed */
@@ -1960,7 +1985,7 @@ static void sdram_program_graphics_frequency(struct sys_info *sysinfo)
                if (voltage == VOLTAGE_1_05)
                        freq = CRCLK_250MHz;
                else
-                       freq = CRCLK_400MHz;
+                       freq = CRCLK_400MHz; /* 1.5V requires 400MHz */
                break;
        case GFX_FREQUENCY_CAP_250MHZ: freq = CRCLK_250MHz; break;
        case GFX_FREQUENCY_CAP_200MHZ: freq = CRCLK_200MHz; break;
@@ -2048,10 +2073,6 @@ static void sdram_program_memory_frequency(struct sys_info *sysinfo)
 {
        u32 clkcfg;
        u8 reg8;
-       u8 offset = 0;
-#ifdef CHIPSET_I945GM
-       offset++;
-#endif
 
        printk(BIOS_DEBUG, "Setting Memory Frequency... ");
 
@@ -2073,9 +2094,9 @@ static void sdram_program_memory_frequency(struct sys_info *sysinfo)
        }
 
        switch (sysinfo->memory_frequency) {
-       case 400: clkcfg |= ((1+offset) << 4); break;
-       case 533: clkcfg |= ((2+offset) << 4); break;
-       case 667: clkcfg |= ((3+offset) << 4); break;
+       case 400: clkcfg |= (2 << 4); break;
+       case 533: clkcfg |= (3 << 4); break;
+       case 667: clkcfg |= (4 << 4); break;
        default: die("Target Memory Frequency Error");
        }
 
@@ -2100,7 +2121,7 @@ vco_update:
        clkcfg |= (1 << 10);
        MCHBAR32(CLKCFG) = clkcfg;
 
-       __asm__ __volatile__ (
+       asm volatile (
                "       movl $0x100, %%ecx\n"
                "delay_update:\n"
                "       nop\n"
@@ -2110,7 +2131,7 @@ vco_update:
                "       loop delay_update\n"
                : /* No outputs */
                : /* No inputs */
-               : "%ecx"
+               : "%ecx", "memory"
                );
 
        clkcfg &= ~(1 << 10);
@@ -2132,7 +2153,7 @@ static void sdram_program_clock_crossing(void)
        /**
         * We add the indices according to our clocks from CLKCFG.
         */
-#ifdef CHIPSET_I945GM
+#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
        static const u32 data_clock_crossing[] = {
                0x00100401, 0x00000000, /* DDR400 FSB400 */
                0xffffffff, 0xffffffff, /*  nonexistant  */
@@ -2140,7 +2161,7 @@ static void sdram_program_clock_crossing(void)
 
                0x08040120, 0x00000000, /* DDR400 FSB533 */
                0x00100401, 0x00000000, /* DDR533 FSB533 */
-               0xffffffff, 0xffffffff, /*  nonexistant  */
+               0x00010402, 0x00000000, /* DDR667 FSB533 - fake values */
 
                0x04020120, 0x00000010, /* DDR400 FSB667 */
                0x10040280, 0x00000040, /* DDR533 FSB667 */
@@ -2177,8 +2198,7 @@ static void sdram_program_clock_crossing(void)
                0xffffffff, 0xffffffff, /*  nonexistant  */
        };
 
-#endif
-#ifdef CHIPSET_I945GC
+#elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC)
        /* i945 G/P */
        static const u32 data_clock_crossing[] = {
                0xffffffff, 0xffffffff, /*  nonexistant  */
@@ -2187,7 +2207,7 @@ static void sdram_program_clock_crossing(void)
 
                0x10080201, 0x00000000, /* DDR400 FSB533 */
                0x00100401, 0x00000000, /* DDR533 FSB533 */
-               0xffffffff, 0xffffffff, /*  nonexistant  */
+               0x00010402, 0x00000000, /* DDR667 FSB533 - fake values */
 
                0xffffffff, 0xffffffff, /*  nonexistant  */
                0xffffffff, 0xffffffff, /*  nonexistant  */
@@ -2209,7 +2229,7 @@ static void sdram_program_clock_crossing(void)
 
                0x00010800, 0x00000402, /* DDR400 FSB533 */
                0x01000400, 0x00000200, /* DDR533 FSB533 */
-               0xffffffff, 0xffffffff, /*  nonexistant  */
+               0x00020904, 0x00000000, /* DDR667 FSB533 - fake values */
 
                0xffffffff, 0xffffffff, /*  nonexistant  */
                0xffffffff, 0xffffffff, /*  nonexistant  */
@@ -2397,7 +2417,7 @@ static void sdram_post_jedec_initialization(struct sys_info *sysinfo)
        if (sysinfo->interleaved) {
 
                reg32 = MCHBAR32(DCC);
-#if CHANNEL_XOR_RANDOMIZATION
+#if CONFIG_CHANNEL_XOR_RANDOMIZATION
                reg32 &= ~(1 << 10);
                reg32 |= (1 << 9);
 #else
@@ -2619,6 +2639,7 @@ static void sdram_thermal_management(void)
         * 0x30/0x32.
         */
 
+       /* TODO This is not implemented yet. Volunteers? */
 }
 
 static void sdram_save_receive_enable(void)
@@ -2650,7 +2671,7 @@ static void sdram_save_receive_enable(void)
        values[3] |= (reg32 >> (24 - 4)) & 0xf0;
 
        /* coreboot only uses bytes 0 - 127 for its CMOS values so far
-        * so we grad bytes 128 - 131 to save the receive enable values
+        * so we grab bytes 128 - 131 to save the receive enable values
         */
 
        for (i=0; i<4; i++)
@@ -2768,10 +2789,9 @@ static void sdram_enable_memory_clocks(struct sys_info *sysinfo)
 {
        u8 clocks[2] = { 0, 0 };
 
-#ifdef CHIPSET_I945GM
+#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
 #define CLOCKS_WIDTH 2
-#endif
-#ifdef CHIPSET_I945GC
+#elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC)
 #define CLOCKS_WIDTH 3
 #endif
        if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED)
@@ -2786,15 +2806,11 @@ static void sdram_enable_memory_clocks(struct sys_info *sysinfo)
        if (sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)
                clocks[1] |= ((1 << CLOCKS_WIDTH)-1) << CLOCKS_WIDTH;
 
-#ifdef OVERRIDE_CLOCK_DISABLE
+#if CONFIG_OVERRIDE_CLOCK_DISABLE
        /* Usually system firmware turns off system memory clock signals
         * to unused SO-DIMM slots to reduce EMI and power consumption.
         * However, the Kontron 986LCD-M does not like unused clock
         * signals to be disabled.
-        * If other similar mainboard occur, it would make sense to make
-        * this an entry in the sysinfo structure, and pre-initialize that
-        * structure in the mainboard's romstage.c main() function.
-        * For now an #ifdef will do.
         */
 
        clocks[0] = 0xf; /* force all clock gate pairs to enable */
@@ -3011,8 +3027,6 @@ void sdram_initialize(int boot_path)
        struct sys_info sysinfo;
        u8 reg8, cas_mask;
 
-       sdram_detect_errors();
-
        printk(BIOS_DEBUG, "Setting up RAM controller.\n");
 
        memset(&sysinfo, 0, sizeof(sysinfo));
@@ -3022,6 +3036,9 @@ void sdram_initialize(int boot_path)
        /* Look at the type of DIMMs and verify all DIMMs are x8 or x16 width */
        sdram_get_dram_configuration(&sysinfo);
 
+       /* If error, do cold boot */
+       sdram_detect_errors(&sysinfo);
+
        /* Check whether we have stacked DIMMs */
        sdram_verify_package_type(&sysinfo);