* drop ich7 include

[coreboot.git] / src / northbridge / intel / i945 / acpi / i945.asl

diff --git a/src/northbridge/intel/i945/acpi/i945.asl b/src/northbridge/intel/i945/acpi/i945.asl
index e6ba95d00dcdc28e145ecb2b42eeb9509f83ef4c..49986f9cef8dcd2c9d96fe963752ea1fbd7c106b 100644 (file)
--- a/src/northbridge/intel/i945/acpi/i945.asl
+++ b/src/northbridge/intel/i945/acpi/i945.asl
@@ -26,35 +26,50 @@ Device (PDRC)
 {
        Name (_HID, EISAID("PNP0C02"))
        Name (_UID, 1)
+
+       // This does not seem to work correctly yet - set values statically for
+       // now.
+       
+       //Name (PDRS, ResourceTemplate() {
+       //      Memory32Fixed(ReadWrite, 0x00000000, 0x00004000, RCRB) // RCBA
+       //      Memory32Fixed(ReadWrite, 0x00000000, 0x00004000, MCHB) // MCHBAR
+       //      Memory32Fixed(ReadWrite, 0x00000000, 0x00001000, DMIB) // DMIBAR
+       //      Memory32Fixed(ReadWrite, 0x00000000, 0x00001000, EGPB) // EPBAR
+       //      Memory32Fixed(ReadWrite, 0x00000000, 0x00000000, PCIE) // PCIE BAR
+       //      Memory32Fixed(ReadWrite, 0xfed20000, 0x00070000, ICHB) // Misc ICH
+       //})
+
        Name (PDRS, ResourceTemplate() {
-               Memory32Fixed(ReadWrite, 0x00000000, 0x00004000, RCRB) // RCBA
-               Memory32Fixed(ReadWrite, 0x00000000, 0x00004000, MCHB) // MCHBAR
-               Memory32Fixed(ReadWrite, 0x00000000, 0x00001000, DMIB) // DMIBAR
-               Memory32Fixed(ReadWrite, 0x00000000, 0x00001000, EGPB) // EPBAR
-               Memory32Fixed(ReadWrite, 0x00000000, 0x00000000, PCIE) // PCIE BAR
-               Memory32Fixed(ReadWrite, 0xfed20000, 0x00070000, ICHB) // Misc ICH
+               Memory32Fixed(ReadWrite, 0xfed1c000, 0x00004000) // RCBA
+               Memory32Fixed(ReadWrite, 0xfed14000, 0x00004000) // MCHBAR
+               Memory32Fixed(ReadWrite, 0xfed18000, 0x00001000) // DMIBAR
+               Memory32Fixed(ReadWrite, 0xfed19000, 0x00001000) // EPBAR
+               Memory32Fixed(ReadWrite, 0xf0000000, 0x04000000) // PCIE BAR
+               Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
+               Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
+               Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
        })
 
        // Current Resource Settings
        Method (_CRS, 0, Serialized)
        {
-               CreateDwordField(PDRS, ^RCRB._BAS, RBR0)
-               ShiftLeft(\_SB.PCI0.LPCB.RCBA, 14, RBR0)
+               //CreateDwordField(PDRS, ^RCRB._BAS, RBR0)
+               //ShiftLeft(\_SB.PCI0.LPCB.RCBA, 14, RBR0)
 
-               CreateDwordField(PDRS, ^MCHB._BAS, MBR0)
-               ShiftLeft(\_SB.PCI0.MCHC.MHBR, 14, MBR0)
+               //CreateDwordField(PDRS, ^MCHB._BAS, MBR0)
+               //ShiftLeft(\_SB.PCI0.MCHC.MHBR, 14, MBR0)
 
-               CreateDwordField(PDRS, ^DMIB._BAS, DBR0)
-               ShiftLeft(\_SB.PCI0.MCHC.DMBR, 12, DBR0)
+               //CreateDwordField(PDRS, ^DMIB._BAS, DBR0)
+               //ShiftLeft(\_SB.PCI0.MCHC.DMBR, 12, DBR0)
 
-               CreateDwordField(PDRS, ^EGPB._BAS, EBR0)
-               ShiftLeft(\_SB.PCI0.MCHC.EPBR, 12, EBR0)
+               //CreateDwordField(PDRS, ^EGPB._BAS, EBR0)
+               //ShiftLeft(\_SB.PCI0.MCHC.EPBR, 12, EBR0)
 
-               CreateDwordField(PDRS, ^PCIE._BAS, PBR0)
-               ShiftLeft(\_SB.PCI0.MCHC.PXBR, 26, PBR0)
+               //CreateDwordField(PDRS, ^PCIE._BAS, PBR0)
+               //ShiftLeft(\_SB.PCI0.MCHC.PXBR, 26, PBR0)
 
-               CreateDwordField(PDRS, ^PCIE._LEN, PSZ0)
-               ShiftLeft(0x10000000, \_SB.PCI0.MCHC.PXSZ, PSZ0)
+               //CreateDwordField(PDRS, ^PCIE._LEN, PSZ0)
+               //ShiftLeft(0x10000000, \_SB.PCI0.MCHC.PXSZ, PSZ0)
 
                Return(PDRS)
        }