Split NORTHBRIDGE_INTEL_I945 into more precise _I945GC and _I945GM

[coreboot.git] / src / northbridge / intel / i945 / Kconfig

diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig
index 041069a369a714a43439f772fff142d648918938..6a8d376e6047a8834176a28303b7beeb8853e02b 100644 (file)
--- a/src/northbridge/intel/i945/Kconfig
+++ b/src/northbridge/intel/i945/Kconfig
@@ -17,12 +17,40 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-config NORTHBRIDGE_INTEL_I945
+config NORTHBRIDGE_INTEL_I945GC
        bool
-       select HAVE_HIGH_TABLES
+       select HAVE_DEBUG_RAM_SETUP
+
+config NORTHBRIDGE_INTEL_I945GM
+       bool
+       select HAVE_DEBUG_RAM_SETUP
+
+if NORTHBRIDGE_INTEL_I945GC || NORTHBRIDGE_INTEL_I945GM
 
 config FALLBACK_VGA_BIOS_ID
        string
        default "8086,27a2"
-       depends on NORTHBRIDGE_INTEL_I945
 
+config CHANNEL_XOR_RANDOMIZATION
+       bool
+       default n
+
+config OVERRIDE_CLOCK_DISABLE
+       bool
+       default n
+       help
+         Usually system firmware turns off system memory clock
+         signals to unused SO-DIMM slots to reduce EMI and power
+         consumption.
+         However, some boards do not like unused clock signals to
+         be disabled.
+
+config MAXIMUM_SUPPORTED_FREQUENCY
+       int
+       default 0
+       help
+         If non-zero, this designates the maximum DDR frequency
+         the board supports, despite what the chipset should be
+         capable of.
+
+endif