-
/* This was originally for the e7500, modified for i855pm
*/
+/* the 855pm uses only
+ * memory type (must be ddr)
+ * number of row addresses, not counting bank addresses
+ * number of column addresses
+ * number of so-dimm banks
+ * ecc, no ecc
+ * refresh rate/type
+ * number banks on each device
+ *
+ * that's it. No other bytes are used.
+ * these are bytes
+ * 2, 3, 4, 5, 11, 12 17
+ */
+
/* converted to C 6/2004 yhlu */
-#define DEBUG_RAM_CONFIG 1
-#define ASM_CONSOLE_LOGLEVEL 10
-#define dumpnorth() dump_pci_device(PCI_DEV(0, 0, 0))
+#define DEBUG_RAM_CONFIG 2
+#undef ASM_CONSOLE_LOGLEVEL
+#define ASM_CONSOLE_LOGLEVEL 8
+#define dumpnorth() dump_pci_device(PCI_DEV(0, 0, 1))
/* DDR DIMM Mode register Definitions */
#define BURST_LENGTH BURST_4
#define BURST_TYPE BURST_INTERLEAVED
#define CAS_LATENCY CAS_2_0
-//#define CAS_LATENCY CAS_2_5
-//#define CAS_LATENCY CAS_1_5
+/*#define CAS_LATENCY CAS_2_5*/
+/*#define CAS_LATENCY CAS_1_5*/
+/* WOW! this could be bad! sets casl to 2 without checking! */
#define MRS_VALUE (MODE_NORM | CAS_LATENCY | BURST_TYPE | BURST_LENGTH)
#define EMRS_VALUE 0x000
uint8_t byte;
int i;
uint32_t result;
-#if DEBUG_RAM_CONFIG >= 2
+#if DEBUG_RAM_CONFIG >=2
print_debug("P:");
print_debug_hex8(value);
print_debug("\r\n");
/* %ecx - initial address to read from */
/* Compute the offset */
dword = value >> 16;
- for(i=0;i<8;i++) {
+ /* for(i=0;i<4;i++) {*/
+ for(i=0;i<1;i++) {
/* Set the ram command */
- byte = pci_read_config8(ctrl->d0, 0x7c);
+ byte = pci_read_config8(ctrl->d0, 0x70);
byte &= 0x8f;
byte |= (uint8_t)(value & 0xff);
- pci_write_config8(ctrl->d0, 0x7c, byte);
+#if DEBUG_RAM_CONFIG
+ print_debug("R:");
+ print_debug_hex8(byte);
+ print_debug("\r\n");
+#endif
+
+ pci_write_config8(ctrl->d0, 0x70, byte);
/* Assert the command to the memory */
#if DEBUG_RAM_CONFIG >= 2
print_debug("\r\n");
#endif
- result = read32(dword);
-
+ result = read32(dword);
+
+#if DEBUG_RAM_CONFIG
+ print_debug("Done\r\n");
+#endif
/* Go to the next base address */
- dword += 0x04000000;
+ dword += 0x0200000;
}
/* The command has been sent to all dimms so get out */
}
-
static inline void RAM_CMD(const struct mem_controller *ctrl, uint32_t command, uint32_t offset) {
uint32_t value = ((offset) << (MD_SHIFT + 16))|((command << 4) & 0x70) ;
do_ram_command(ctrl, value);
/* Read the cas latency setting */
uint8_t byte;
uint32_t dword;
- byte = pci_read_config8(ctrl->d0, 0x78);
+ byte = pci_read_config8(ctrl->d0, 0x60);
/* Transform it into the form expected by SDRAM */
- dword = ram_cas_latency[(byte>>4) & 3];
-
+ dword = ram_cas_latency[(byte>>5) & 1];
+#warning RAM_MRS -- using BROKEN hard-wired CAS 2.0. FIX ME SOON
+/*
+ */
value |= (dword<<(16+MD_SHIFT));
value |= (MODE_NORM | BURST_TYPE | BURST_LENGTH) << (16+MD_SHIFT);
static void RAM_NORMAL(const struct mem_controller *ctrl) {
uint8_t byte;
- byte = pci_read_config8(ctrl->d0, 0x7c);
+ byte = pci_read_config8(ctrl->d0, 0x70);
byte &= 0x8f;
byte |= (RAM_COMMAND_NORMAL << 4);
- pci_write_config8(ctrl->d0, 0x7c, byte);
+ pci_write_config8(ctrl->d0, 0x70, byte);
}
static void RAM_RESET_DDR_PTR(const struct mem_controller *ctrl) {
static void ENABLE_REFRESH(const struct mem_controller *ctrl)
{
uint32_t dword;
- dword = pci_read_config32(ctrl->d0, 0x7c);
+ dword = pci_read_config32(ctrl->d0, 0x70);
dword |= (1 << 29);
- pci_write_config32(ctrl->d0, 0x7c, dword);
+ pci_write_config32(ctrl->d0, 0x70, dword);
}
/*
* granularity.
*/
/* Conservatively say each row has 32MB of ram, we will fix this up later */
- 0x60, 0x00000000, (0x01 << 0) | (0x02 << 8) | (0x03 << 16) | (0x04 << 24),
+ 0x40, 0x00000000, (0x01 << 0) | (0x02 << 8) | (0x03 << 16) | (0x04 << 24),
/* DRA - DRAM Row Attribute Register
* 0x70 Row 0,1
* 0x71 Row 2,3
(((0<<3)|(0<<0))<<28),
*/
/* DRT - DRAM Time Register
- * 0x78
- * [31:31] Additional CKE to CS Clock for Read/Write
- * [30:30] Additional CKE to CS clock for Precharge/Activate
- * [29:29] Back to Back Write-Read Turn Around
- * Intel recommends set to 1
+ * 0x60
+ * [31:31] tWTR -- MBZ
+ * [30:30] tWR 0 is 2, 1 is 3 clocks
+ * [29:28] back to back write-read commands spacing
+ * different rows
+ * 00 4, 01 3, 10 2, 11 reserved
+ *
+ * [27:26] same or different
+ * CL + .5x BL + TA(RD-WR) - DQSS
+ * wow that's hard!
+ * 00 7, 01 6, 10 5, 11 4
+ * 00 4, 01 3, 10 2, 11 reserved
*
- * [28:28] Back to Back Read-Write Turn Around
- * Intel recommends 0 for CL 2.5 and 1 for CL 2
+ * [25:25] Back to Back Read-read spacing
+ * .5xBL + TA(RD-RD)
+ * 0 4 , 1 3
*
- * [27:27] Back to Back Read Turn Around
- * Intel recommends 1 for all configs
- *
- * [26:24] Read Delay (tRD)
- * 000 == 9 clocks
- * 001 == 8 clocks
- * 010 == 7 clocks
- * 011 == 6 clocks
- * 100 == 5 clocks
- * 101 == 4 clocks
- * 110 == 3 clocks
- * Others == Reserved
- * [23:20] Reserved
- * [19:19] No Wake for DDR page closes
- * 0 is default
- * [18:16] Page Close Counter
- * 000 == infinite
- * 010 == 8-15 clocks
- * 011 == 16-31 clocks
- * 100 == 64-127 clocks
- * 101 == 128-255 clocks
- * 110 == 192-383 clocks
- * 111 == 255-510 clocks
+ * [24:15] Reserved
*
- * [15:12] Reserved
- * [11:11] DQS Slave DLL Dynamic Management
- * power saving, when set to 1, slave DLLS disabled
- * we'll leave it at 0 for now
+ * [14:12] Refresh cycle time
+ * 000 14, 001 13, 010 12, 011 11, 100 10, 101 9, 110 8, 111 7
+ *
+ * [11:11] tRAS, max
+ * 0 120 us, 1 reserved
+ *
* [10:09] Active to Precharge (tRAS)
- * 00 == 7 clocks
- * 01 == 6 clocks
- * 10 == 5 clocks
- * 11 == Reserved
- * [08:06] Reserved
- * [05:04] Cas Latency (tCL)
+ * 00 == 8 clocks
+ * 01 == 7 clocks
+ * 10 == 6 clocks
+ * 11 == 5 clocks
+ * [08:07] Reserved
+ * [06:05] Cas Latency (tCL)
* 00 == 2.5 Clocks
* 01 == 2.0 Clocks (default)
- * 10 == 1.5 Clocks
+ * 10 == Reserved
* 11 == Reserved
- * [03:03] Reserved
- * [02:02] Ras# to Cas# Delay (tRCD)
- * 0 == 3 DRAM Clocks
- * 1 == 2 DRAM Clocks
- * [01:01] Reserved
- * [00:00] DRAM RAS# to Precharge (tRP)
- * 0 == 3 DRAM Clocks
- * 1 == 2 DRAM Clocks
+ * [04:04] Reserved
+ * [03:02] Ras# to Cas# Delay (tRCD)
+ * 00 == 4 DRAM Clocks
+ * 01 == 3 DRAM Clocks
+ * 10 == 2 DRAM Clocks
+ * 11 == reserved
+ * [01:00] DRAM RAS# to Precharge (tRP)
+ * 00 == 4 DRAM Clocks
+ * 01 == 3 DRAM Clocks
+ * 10 == 2 DRAM Clocks
+ * 11 == reserved
*/
-#define DRT_CAS_2_5 (0<<4)
-#define DRT_CAS_2_0 (1<<4)
-#define DRT_CAS_1_5 (2<<4)
-#define DRT_CAS_MASK (3<<4)
+#define DRT_CAS_2_5 (0<<5)
+#define DRT_CAS_2_0 (1<<5)
+#define DRT_CAS_MASK (3<<5)
#if CAS_LATENCY == CAS_2_5
#define DRT_CL DRT_CAS_2_5
#elif CAS_LATENCY == CAS_2_0
#define DRT_CL DRT_CAS_2_0
-#elif CAS_LATENCY == CAS_1_5
-#define DRT_CL DRT_CAS_1_5
#endif
- /* Most unaggressive settings possible */
- /* clear bits 26:24,18:16,11,10:9,5:4,2:2,0 */
- /* ~ (7<<26)|(7<<18)|(1<<11)|(3<<10)|(3<<5)|(1<<2)|1 */
-// 0x78, 0xc0fff8c4, (1<<29)|(1<<28)|(1<<27)|(2<<24)|(2<<9)|DRT_CL|(1<<3)|(1<<1)|(1<<0),
-// 0x78, 0xc0f8f8c0, (1<<29)|(1<<28)|(1<<27)|(1<<24)|(1<<16)|(2<<9)|DRT_CL|(1<<3)|(3<<1)|(1<<0),
-// 0x78, 0xc0f8f9c0, (1<<29)|(1<<28)|(1<<27)|(1<<24)|(1<<16)|(2<<9)|DRT_CL|(1<<3)|(3<<1)|(1<<0),
- 0x78, ~((7<<26)|(7<<18)|(1<<11)|(3<<10)|(3<<5)|(1<<2)|1),
- (1<<29)|(1<<28)|(9<<26)|(0<<18)|(0<<11)|(0<<10)|(0<<5)|(0<<2)|(0<<0),
+ /* bios is 0x2a004425 */
+ /* default hardware is 18004425 */
+ /* no setting for now */
/* FDHC - Fixed DRAM Hole Control
* 0x97
* 10 == Write Only (Writes to DRAM, Reads to memory mapped I/O space)
* 11 == Normal (All Access go to DRAM)
*/
- 0x90, 0xcccccf7f, (0x00 << 0) | (0x30 << 8) | (0x33 << 16) | (0x33 << 24),
- 0x94, 0xcccccccc, (0x33 << 0) | (0x33 << 8) | (0x33 << 16) | (0x33 << 24),
+ /* 0x90, 0xcccccf7f, (0x00 << 0) | (0x30 << 8) | (0x33 << 16) | (0x33 << 24),*/
+ /*0x94, 0xcccccccc, (0x33 << 0) | (0x33 << 8) | (0x33 << 16) | (0x33 << 24),*/
/* FIXME why was I attempting to set a reserved bit? */
* [03:01] Reserved
* [00:00] DRAM type --hardwired to 1 to indicate DDR
*/
-// .long 0x7c, 0xffcefcff, (1<<22)|(2 << 20)|(1 << 16)| (0 << 8),
-// .long 0x7c, 0xff8cfcff, (1<<22)|(2 << 20)|(1 << 17)|(1 << 16)| (0 << 8),
-// .long 0x7c, 0xff80fcff, (1<<22)|(2 << 20)|(1 << 18)|(1 << 17)|(1 << 16)| (0 << 8),
-// 0x7c, 0xff82fcff, (1<<22)|(2 << 20)|(1 << 18)|(1 << 16)| (0 << 8),
- 0x7c, 0xff82f8ff, (1<<22)|(2 << 20)|(1 << 18)|(1 << 16)| (0 << 8),
+ 0x70, 0xdf0f6c7f, 0,
+ /* undocumnted shit */
+ 0x80, 0, 0xaf0031,
};
* Which are a triple of configuration regiser, mask, and value.
*
*/
-/* from 1M or 512K */
-#define RCOMP_MMIO 0x100000
-
- /* DDR RECOMP table */
-
-static const long ddr_rcomp_1[] = {
- 0x44332211, 0xc9776655, 0xffffffff, 0xffffffff,
- 0x22111111, 0x55444332, 0xfffca876, 0xffffffff,
-};
-static const long ddr_rcomp_2[] = {
- 0x00000000, 0x76543210, 0xffffeca8, 0xffffffff,
- 0x21000000, 0xa8765432, 0xffffffec, 0xffffffff,
-};
-static const long ddr_rcomp_3[] = {
- 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
- 0x88888888, 0x88888888, 0x88888888, 0x88888888,
-};
-
-#define rcomp_init_str "Setting RCOMP registers.\r\n"
static void write_8dwords(uint32_t src_addr, uint32_t dst_addr) {
int i;
}
}
-//#define SLOW_DOWN_IO inb(0x80);
+/*#define SLOW_DOWN_IO inb(0x80);*/
#define SLOW_DOWN_IO udelay(40);
-static void ram_set_rcomp_regs(const struct mem_controller *ctrl) {
- uint32_t dword;
-#if DEBUG_RAM_CONFIG
- print_debug(rcomp_init_str);
-#endif
-
- /*enable access to the rcomp bar */
- /* for e7501 they also set bit 31 ... */
- dword = pci_read_config32(ctrl->d0, 0x0f4);
- dword |= 1<<22;
- pci_write_config32(ctrl->d0, 0x0f4, dword);
-
-
- /* Set the MMIO address to 512K */
- pci_write_config32(ctrl->d0, 0x14, RCOMP_MMIO);
-
- dword = read32(RCOMP_MMIO + 0x20);
- dword |= (1<<9);
- write32(RCOMP_MMIO + 0x20, dword);
-
-#ifdef NOTNOW
- /* Begin to write the RCOMP registers */
-
- write8(RCOMP_MMIO + 0x2c, 0xff);
- write32(RCOMP_MMIO + 0x30, 0x01040444);
- write8(RCOMP_MMIO + 0x34, 0x04);
- write32(RCOMP_MMIO + 0x40, 0);
- write16(RCOMP_MMIO + 0x44, 0);
- write16(RCOMP_MMIO + 0x48, 0);
- write16(RCOMP_MMIO + 0x50, 0);
- write_8dwords((uint32_t)ddr_rcomp_1, RCOMP_MMIO + 0x60);
- write_8dwords((uint32_t)ddr_rcomp_2, RCOMP_MMIO + 0x80);
- write_8dwords((uint32_t)ddr_rcomp_2, RCOMP_MMIO + 0xa0);
- write_8dwords((uint32_t)ddr_rcomp_2, RCOMP_MMIO + 0x140);
- write_8dwords((uint32_t)ddr_rcomp_2, RCOMP_MMIO + 0x1c0);
- write_8dwords((uint32_t)ddr_rcomp_3, RCOMP_MMIO + 0x180);
-
-#if 0 /* Print the RCOMP registers */
- movl $RCOMP_MMIO, %ecx
-1: movl %ecx, %eax
- andb $0x0f, %al
- jnz 2f
- CONSOLE_INFO_TX_CHAR($'\r')
- CONSOLE_INFO_TX_CHAR($'\n')
- CONSOLE_INFO_TX_HEX32(%ecx)
- CONSOLE_INFO_TX_CHAR($' ')
- CONSOLE_INFO_TX_CHAR($'-')
- CONSOLE_INFO_TX_CHAR($' ')
-2: movl (%ecx), %eax
- CONSOLE_INFO_TX_HEX32(%eax)
- CONSOLE_INFO_TX_CHAR($' ')
- addl $4, %ecx
- cmpl $(RCOMP_MMIO + 0x1e0), %ecx
- jnz 1b
- CONSOLE_INFO_TX_CHAR($'\r')
- CONSOLE_INFO_TX_CHAR($'\n')
-#endif
-
- dword = read32(RCOMP_MMIO + 0x20);
- dword &= ~(3);
- dword |= 1;
- write32(RCOMP_MMIO + 0x20, dword);
-
- /* Wait 40 usec */
- SLOW_DOWN_IO;
-
- /* unblock updates */
- dword = read32(RCOMP_MMIO + 0x20);
- dword &= ~(1<<9);
- write32(RCOMP_MMIO+0x20, dword);
- dword |= (1<<8);
- write32(RCOMP_MMIO+0x20, dword);
- dword &= ~(1<<8);
- write32(RCOMP_MMIO+0x20, dword);
-
- /* Wait 40 usec */
- SLOW_DOWN_IO;
-#endif
- /*disable access to the rcomp bar */
- dword = pci_read_config32(ctrl->d0, 0x0f4);
- dword &= ~(1<<22);
- pci_write_config32(ctrl->d0, 0x0f4, dword);
-
-}
static void ram_set_d0f0_regs(const struct mem_controller *ctrl) {
#if DEBUG_RAM_CONFIG
- dumpnorth();
+ //dumpnorth();
#endif
int i;
int max;
- max = sizeof(register_values)/sizeof(register_values[0]);
+ max = ARRAY_SIZE(register_values);
for(i = 0; i < max; i += 3) {
uint32_t reg;
-#if DEBUG_RAM_CONFIG
+#if DEBUG_RAM_CONFIG >=2
print_debug_hex32(register_values[i]);
print_debug(" <-");
print_debug_hex32(register_values[i+2]);
#endif
}
static void sdram_set_registers(const struct mem_controller *ctrl){
- ram_set_rcomp_regs(ctrl);
ram_set_d0f0_regs(ctrl);
}
* a multiple of 4MB. The way we do it now we can size both
* sides of an assymetric dimm.
*/
- value = spd_read_byte(device, 3); /* rows */
- if (value < 0) goto hw_err;
-// if ((value & 0xf) == 0) goto val_err;
- sz.side1 += value & 0xf;
-
- value = spd_read_byte(device, 4); /* columns */
- if (value < 0) goto hw_err;
-// if ((value & 0xf) == 0) goto val_err;
- sz.side1 += value & 0xf;
-
- value = spd_read_byte(device, 17); /* banks */
- if (value < 0) goto hw_err;
-// if ((value & 0xff) == 0) goto val_err;
- value &=0xff;
- sz.side1 += log2(value);
-
- /* Get the module data width and convert it to a power of two */
- value = spd_read_byte(device, 7); /* (high byte) */
- if (value < 0) goto hw_err;
- value &= 0xff;
- value <<= 8;
-
- low = spd_read_byte(device, 6); /* (low byte) */
- if (low < 0) goto hw_err;
- value |= (low & 0xff);
-// if ((value != 72) && (value != 64)) goto val_err;
- sz.side1 += log2(value);
-
- /* side 2 */
- value = spd_read_byte(device, 5); /* number of physical banks */
- if (value < 0) goto hw_err;
- if (value == 1) goto out;
-// if (value != 2) goto val_err;
-
- /* Start with the symmetrical case */
- sz.side2 = sz.side1;
-
- value = spd_read_byte(device, 3); /* rows */
- if (value < 0) goto hw_err;
- if ((value & 0xf0) == 0) goto out; /* If symmetrical we are done */
- sz.side2 -= (value & 0x0f); /* Subtract out rows on side 1 */
- sz.side2 += ((value >> 4) & 0x0f); /* Add in rows on side 2 */
-
- value = spd_read_byte(device, 4); /* columns */
- if (value < 0) goto hw_err;
-// if ((value & 0xff) == 0) goto val_err;
- sz.side2 -= (value & 0x0f); /* Subtract out columns on side 1 */
- sz.side2 += ((value >> 4) & 0x0f); /* Add in columsn on side 2 */
- goto out;
-
+ /* the hell with that! just use byte 31 -- rgm */
+ value = spd_read_byte(device, 31); /* size * 4 MB */
+ value = log2(value);
+ /* this is in 4 MB chunks, or 32 MBits chunks.
+ * log base 2 of 32 Mbits is log2 of (32*1024*1024) is 25
+ * so add 25
+ */
+ value += 25;
+ sz.side1 = value;
+ sz.side2 = 0;
+#if DEBUG_RAM_CONFIG
+ print_debug("returned size log 2 in bits is :");
+ print_debug_hex32(value);
+ print_debug("\r\n");
+#endif
+ goto out;
val_err:
die("Bad SPD value\r\n");
/* If an hw_error occurs report that I have no memory */
*/
static long spd_set_row_attributes(const struct mem_controller *ctrl, long dimm_mask) {
int i;
- uint32_t dword=0;
+ uint16_t word=0x7777;
int value;
print_err("unsupported page size\r\n");
}
- /* double because I have 2 channels */
- sz.side1++;
-
/* Convert to the format needed for the DRA register */
+ /* subtract 3 (there are 8 bytes)
+ * then subtract 11
+ * (since 12 bit size should map to a value of 1)
+ * so subtract 14 total
+ */
sz.side1-=14;
- /* Place in the %ebp the dra place holder */ //i
- dword |= sz.side1<<(i<<3);
+ /* Place in the %ebp the dra place holder */ /*i*/
+ word &= ~(7<<i);
+ word |= sz.side1<<(i<<3);
/* Test to see if the second side is present */
print_err("unsupported page size\r\n");
}
- /* double because I have 2 channels */
- sz.side2++;
-
/* Convert to the format needed for the DRA register */
sz.side2-=14;
- /* Place in the %ebp the dra place holder */ //i
- dword |= sz.side2<<((i<<3) + 4 );
+ /* Place in the %ebp the dra place holder */ /*i*/
+ word &= ~(7<<i);
+ word |= sz.side2<<((i<<3) + 4 );
}
}
-
- /* Now add the SDRAM chip width to the DRA */
- struct dimm_width wd;
- wd = sdram_spd_get_width(ctrl->channel0[i]);
-
-#if DEBUG_RAM_CONFIG
- print_debug("width =");
- print_debug_hex32(wd.side1);
- print_debug(" ");
- print_debug_hex32(wd.side2);
- print_debug("\r\n");
-#endif
-
- if(wd.side1 == 0) continue;
- if(wd.side1 == 4) {
- /* Enable an x4 device */
- dword |= 0x08 << (i<<3);
- }
-
- if(wd.side2 == 0) continue;
- if(wd.side2 == 4) {
- /* Enable an x4 device */
- dword |= 0x08 << ((i<<3 ) + 4);
- }
-
/* go to the next DIMM */
}
/* Write the new row attributes register */
- pci_write_config32(ctrl->d0, 0x70, dword);
+ pci_write_config32(ctrl->d0, 0x50, word);
return dimm_mask;
}
-#if 0
- /*
- * Routine: sdram_read_paired_byte
- * Arguments: %esp return address
- * %bl device on the smbus to read from
- * %bh address on the smbus to read
- * Results:
- * zf clear
- * byte read in %al
- * On Error:
- * zf set
- * %eax trashed
- *
- * Preserved: %ebx, %esi, %edi
- *
- * Trashed: %eax, %ecx, %edx, %ebp, %esp, %eflags
- * Used: %eax, %ebx, %ecx, %edx, %esp, %eflags
- *
- * Effects: Reads two spd bytes from both ram channesl
- * and errors if they are not equal.
- * It then returns the equal result.
- */
-static spd_read_paired_byte () {
- movl %esp, %ebp
- CALLSP(smbus_read_byte)
- setnz %cl
- movb %al, %ch
- addb $(SMBUS_MEM_CHANNEL_OFF), %bl
- CALLSP(smbus_read_byte)
- movb %ch, %ah
- setnz %ch
- subb $(SMBUS_MEM_CHANNEL_OFF), %bl
-
- /* See if dimms on both sides are equally present */
- cmp %cl, %ch
- jne sdram_presence_mismatch
-
- /* Leave if I have no data */
- testb %cl, %cl
- jz spd_verify_byte_out
-
- /* Verify the data is identical */
- cmp %ah, %al
- jne sdram_value_mismatch
-
- /* Clear the zero flag */
- testb %cl, %cl
-spd_verify_byte_out:
- movl %ebp, %esp
- RETSP
-}
-
- /*
- * Routine: spd_verify_dimms
- * Arguments: none
- * Results: none
- * Preserved: none
- * Trashed: %eax, %ebx, %ecx, %edx, %ebp, %esi, %edi, %esp, %eflags
- * Used: %eax, %ebx, %ecx, %edx, %ebp, %esi, %edi, %esp, %eflags
- *
- * Effects:
- * - Verify all interesting spd information
- * matches for both dimm channels.
- * - Additional error checks that can be easily done
- * here are computed as well, so I don't need to
- * worry about them later.
- */
-static spd_verify_dimms() {
- movl $(SMBUS_MEM_DEVICE_START), %ebx
-spd_verify_dimm:
- /* Verify this is DDR SDRAM */
- movb $2, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_verify_next_dimm
- cmpb $7, %al
- jne invalid_dimm_type
-
- /* Verify the row addresses */
- movb $3, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
- testb $0x0f, %al
- jz spd_invalid_data
-
- /* Column addresses */
- movb $4, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
- testb $0xf, %al
- jz spd_invalid_data
-
- /* Physical Banks */
- movb $5, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
- cmp $1, %al
- jb spd_invalid_data
- cmp $2, %al
- ja spd_invalid_data
-
- /* Module Data Width */
- movb $7, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
- cmpb $0, %al
- jne spd_invalid_data
-
- movb $6, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
- cmpb $64, %al
- je 1f
- cmpb $72, %al
- je 1f
- jmp spd_unsupported_data
-1:
-
- /* Cycle time at highest CAS latency CL=X */
- movb $9, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
-
- /* SDRAM type */
- movb $11, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
-
- /* Refresh Interval */
- movb $12, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
-
- /* SDRAM Width */
- movb $13, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
- andb $0x7f, %al
- cmpb $4, %al
- je 1f
- cmpb $8, %al
- je 1f
- jmp spd_unsupported_data
-1:
-
- /* Back-to-Back Random Column Accesses */
- movb $15, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
- testb %al, %al
- jz spd_invalid_data
- cmpb $4, %al
- ja spd_unsupported_data
-
- /* Burst Lengths */
- movb $16, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
- testb $(1<<2), %al
- jz spd_unsupported_data
-
- /* Logical Banks */
- movb $17, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
- testb %al, %al
- jz spd_invalid_data
-
- /* Supported CAS Latencies */
- movb $18, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
- testb $(1 << 1), %al /* CL 1.5 */
- jnz 1f
- testb $(1 << 2), %al /* CL 2.0 */
- jnz 1f
- testb $(1 << 3), %al /* CL 2.5 */
- jnz 1f
- jmp spd_unsupported_data
-1:
-
- /* Cycle time at Cas Latency (CLX - 0.5) */
- movb $23, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
-
- /* Cycle time at Cas Latency (CLX - 1.0) */
- movb $26, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
-
- /* tRP Row precharge time */
- movb $27, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
- testb $0xfc, %al
- jz spd_invalid_data
-
-
- /* tRCD RAS to CAS */
- movb $29, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
- testb $0xfc, %al
- jz spd_invalid_data
-
- /* tRAS Activate to Precharge */
- movb $30, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
- testb %al, %al
- jz spd_invalid_data
-
- /* Module Bank Density */
- movb $31, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
- testb $(1<<2), %al /* 16MB */
- jnz spd_unsupported_data
- testb $(1<<3), %al
- jnz spd_unsupported_data /* 32MB */
-
- /* Address and Command Hold Time After Clock */
- movb $33, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
-
-spd_verify_next_dimm:
- /* go to the next DIMM */
- addb $(SMBUS_MEM_DEVICE_INC), %bl /* increment the smbus device */
- cmpb $SMBUS_MEM_DEVICE_END, %bl
- jbe spd_verify_dimm
-spd_verify_dimms_out:
- RET_LABEL(spd_verify_dimms)
-}
-#endif
#define spd_pre_init "Reading SPD data...\r\n"
#define spd_pre_set "setting based on SPD data...\r\n"
#define spd_post_init "done\r\n"
* 7.8us -> 7.8us
* 31.3s -> 15.6us
* 62.5us -> 15.6us
- * 125us -> 64us
+ * 125us -> 15.6us
*/
- 1, 0xff, 2, 1, 1, 3
+ 1, 0xff, 2, 1, 1, 1
};
#define MAX_SPD_REFRESH_RATE 5
int value;
uint32_t ecx;
uint32_t edx;
+ /* on this chipset we only do refresh "slow" or "fast" for now */
+ /* we start out assuming "slow" (15.6 microseconds) */
+ uint32_t refrate = 1; /* better than 7.8 */
/* Read the inititial state */
- dword = pci_read_config32(ctrl->d0, 0x7c);
+ dword = pci_read_config32(ctrl->d0, 0x70);
+ /* WTF? */
+ /*dword |= 0x10000;*/
+#if 0 /* DEBUG_RAM_CONFIG*/
+ print_debug("spd_detect_dimms: 0x70.l is:");
+ print_debug_hex32(dword);
+ print_debug("\r\n");
+#endif
#if 0
/* Test if ECC cmos option is enabled */
- movb $RTC_BOOT_BYTE, %al
- outb %al, $0x70
- inb $0x71, %al
- testb $(1<<2), %al
- jnz 1f
/* Clear the ecc enable */
- andl $~(3 << 20), %esi
1:
#endif
value = spd_read_byte(ctrl->channel0[i], 11); /* SDRAM type */
if(value < 0) continue;
if(value !=2 ) {
+#if DEBUG_RAM_CONFIG
+ print_debug("spd_detect_dimms:\r\n");
+#endif
/* Clear the ecc enable */
dword &= ~(3 << 20);
+#if 0 &&DEBUG_RAM_CONFIG
+ print_debug("spd_detect_dimms: no ecc so set:");
+ print_debug_hex32(dword);
+ print_debug("\r\n");
+#endif
+
}
value = spd_read_byte(ctrl->channel0[i], 12); /* SDRAM refresh rate */
if(value < 0 ) continue;
value &= 0x7f;
if(value > MAX_SPD_REFRESH_RATE) { print_err("unsupported refresh rate\r\n");}
-// if(value == 0xff) { print_err("unsupported refresh rate\r\n");}
-
- ecx = refresh_rate_index[value];
-
- /* Isolate the old refresh rate setting */
- /* Load the refresh rate ranks */
- edx = refresh_rate_rank[(dword >> 8) & 3]<<8;
- edx |= refresh_rate_rank[ecx] & 0xff;
-
- /* See if the new refresh rate is more conservative than the old
- * refresh rate setting. (Lower ranks are more conservative)
- */
- if((edx & 0xff)< ((edx >> 8) & 0xff) ) {
- /* Clear the old refresh rate */
- dword &= ~(3<<8);
- /* Move in the new refresh rate */
- dword |= (ecx<<8);
- }
+/* if(value == 0xff) { print_err("unsupported refresh rate\r\n");}*/
+#if DEBUG_RAM_CONFIG
+ print_debug("spd_detect_dimms: ref rate index:");
+ print_debug_hex8(value);
+ print_debug("\r\n");
+#endif
+ if (value == 2) /* have to go faster */
+ refrate = 2;
+#if 0 &&DEBUG_RAM_CONFIG
+ print_debug("spd_detect_dimms: dword is now w/refresh:");
+ print_debug_hex32(dword);
+ print_debug("\r\n");
+#endif
+ /* no applicability here but there are similar things
+ * we'll try later.
+ */
+#if 0
value = spd_read_byte(ctrl->channel0[i], 33); /* Address and command hold time after clock */
if(value < 0) continue;
if(value >= 0xa0) { /* At 133Mhz this constant should be 0x75 */
dword &= ~(1<<16); /* Use two clock cyles instead of one */
}
+#endif
/* go to the next DIMM */
}
+ /* set the refrate now */
+ dword |= (refrate << 7);
/* Now write the controller mode */
- pci_write_config32(ctrl->d0, 0x7c, dword);
+ pci_write_config32(ctrl->d0, 0x70, dword);
return dimm_mask;
/* Read the inititial state */
dword = pci_read_config32(ctrl->d0, 0x8c);
-#if 0
-# Intel clears top bit here, should we?
-# No the default is on and for normal timming it should be on. Tom Z
+/*
+ Intel clears top bit here, should we?
+ No the default is on and for normal timming it should be on. Tom Z
andl $0x7f, %esi
-#endif
-
+ */
for(i = 0; i < DIMM_SOCKETS; i++) {
if (!(dimm_mask & (1 << i))) {
* Steven James 02/06/2003
*/
-//# .byte 0x05, 0x01, 0x06
-//# .byte 0xb5, 0xb1, 0xb6
+/*# .byte 0x05, 0x01, 0x06 */
+/*# .byte 0xb5, 0xb1, 0xb6 */
0x0, 0x0bb1, 0x0662 /* RCVEN */
};
static const uint16_t cas_latency_80_4dimms[] = {
static const uint8_t cas_latency_78[] = {
- DRT_CAS_1_5, DRT_CAS_2_0, DRT_CAS_2_5
+ DRT_CAS_2_0, DRT_CAS_2_5
};
static long spd_set_cas_latency(const struct mem_controller *ctrl, long dimm_mask) {
/* Initially allow cas latencies 2.5, 2.0
* which the chipset supports.
*/
- uint32_t dword = (1<<3)| (1<<2);// esi
+ uint32_t dword = (1<<3)| (1<<2);/* esi*/
uint32_t edi;
uint32_t ecx;
unsigned device;
/* After all of the arduous calculation setup with the fastest
* cas latency I can use.
*/
- value = __builtin_bsf(dword); // bsrl = log2 how about bsfl?
+ value = __builtin_bsf(dword); /* bsrl = log2 how about bsfl?*/
if(value ==0 ) return -1;
ecx = value -1;
dword |= (1<<26);
/* the rest of the references are words */
-// ecx<<=1; // don't need shift left, because we already define that in u16 array
+/* ecx<<=1; // don't need shift left, because we already define that in u16 array*/
pci_write_config32(ctrl->d0, 0x88, dword);
}
+static const unsigned int bustimings[8] = {
+ /* first four are for GM part */
+ 266, 200, 200, -1,
+ /* and then the GME part */
+ 266, 200, 200, 333
+};
+
static long spd_set_dram_timing(const struct mem_controller *ctrl, long dimm_mask) {
/* Walk through all dimms and find the interesection of the
* supported dram timings.
uint32_t dword;
int value;
+ /* well, shit. Intel has not seen fit to document the observed
+ * setting for these bits. On my chipset it is 3 right now, and
+ * that's not in the table documented for this chip.
+ * What a shame. We will assume 133 mhz I guess? not sure.
+ * also they say in one place it is two bits and in another
+ * they say it is 3 bits! we'll assume two bits, that's
+ * the only one that makes sense.
+ */
+ uint32_t rambusfrequency;
+ uint32_t ramindex;
+
+ /* what kind of chip is it? */
+ /* only bit that really matters is high order bit ... */
+ /* here is a problem with the memory controller struct ...
+ * ram control is spread across d0/d1 on this part!
+ */
+ ramindex = pci_read_config8(PCI_DEV(0,0,0), 0x44);
+ ramindex >>= 5;
+
+ /* compute the index into the table. Use the type of chip
+ * as the high order bit and the 0:0.3:c0 & 7 as the low
+ * order four bits.
+ */
+
+ ramindex |= pci_read_config8(PCI_DEV(0,0,3), 0xc0) & 7;
+ /* we now have an index into the clock rate table ... */
+
+ rambusfrequency = bustimings[ramindex];
+
/* Read the inititial state */
- dword = pci_read_config32(ctrl->d0, 0x78);
-#if 0
-# Intel clears top bit here, should we?
-# No the default is on and for normal timming it should be on. Tom Z
- andl $0x7f, %esi
+ dword = pci_read_config32(ctrl->d0, 0x60);
+#if DEBUG_RAM_CONFIG >= 10
+ print_debug("spd_detect_dimms: bus timing index: ");
+ print_debug_hex32(ramindex);
+ print_debug(" and speed ");
+ print_debug_hex32(rambusfrequency);
+ print_debug("\r\n");
#endif
+
+ /* for now, since we are on deadline, set to "known good" and
+ * fix later.
+ */
+ pci_write_config32(ctrl->d0, 0x60, 0x2a004425);
+ return dimm_mask;
+
+/*
+ Intel clears top bit here, should we?
+ No the default is on and for normal timming it should be on. Tom Z
+ andl $0x7f, %esi
+ */
-
+
+/* HERE. WHat's the frequency kenneth? */
for(i = 0; i < DIMM_SOCKETS; i++) {
if (!(dimm_mask & (1 << i))) {
continue;
dword |= (1<<29);
}
- pci_write_config32(ctrl->d0, 0x78, dword);
+ pci_write_config32(ctrl->d0, 0x60, dword);
return dimm_mask;
dimm_mask |= (1 << i);
}
}
-#if 0
- device = ctrl->channel1[i];
- if (device) {
- byte = spd_read_byte(ctrl->channel1[i], 2);
- if (byte == 7) {
- dimm_mask |= (1 << (i + DIMM_SOCKETS));
- }
- }
-#endif
}
-#if 1
- i = (dimm_mask>>DIMM_SOCKETS);
- if(i != (dimm_mask & ( (1<<DIMM_SOCKETS) - 1) ) ) {
- die("now we only support dual channel\r\n");
- }
-
-#endif
return dimm_mask;
}
uint32_t dch;
uint8_t byte;
+ /* I think size2 is always 0 ... */
/* Double the size if we are using dual channel memory */
-// if (is_dual_channel(ctrl)) {
- /* Since I have 2 identical channels double the sizes */
- sz.side1++ ;
- sz.side2++;
-// }
-
if (sz.side1 != sz.side2) {
sz.side2 = 0;
}
-
- /* Make certain side1 of the dimm is at least 64MB */
- if (sz.side1 >= (25 + 4)) {
- memsz += (1 << (sz.side1 - (25 + 4)) ) ;
- }
+
+
+ /* Make certain side1 of the dimm is at least 32MB */
+ /* This 28 is weird.
+ * sz.size1 is log2 size in bits.
+ * so what's 28? So think of it as this:
+ * in log2 space: 10 + 10 + 8, i.e. 1024 * 1024 * 256 or
+ * 256 Mbits, or 32 Mbytes.
+ */
+ /* this is from the e7500 code and it's just wrong for small dimes (< 64 MB)
+ * However, realistically, this case will never happen! the dimms are all bigger ...
+ * so skip the conditional completely.
+ * if (sz.side1 >= (28)) { }
+ */
+ memsz += (1 << (sz.side1 - (28)) ) ;
+
/* Write the size of side 1 of the dimm */
+ #if DEBUG_RAM_CONFIG
+ print_debug("Write size ");
+ print_debug_hex8(memsz);
+ print_debug(" to ");
+ print_debug_hex8(0x40 + index);
+ print_debug("\r\n");
+#endif
byte = memsz;
- pci_write_config8(ctrl->d0, 0x60+(index<<1), byte);
+ pci_write_config8(ctrl->d0, 0x40+index, byte);
- /* Make certain side2 of the dimm is at least 64MB */
- if (sz.side2 >= (25 + 4)) {
- memsz += (1 << (sz.side2 - (25 + 4)) ) ;
- }
-
- /* Write the size of side 2 of the dimm */
- byte = memsz;
- pci_write_config8(ctrl->d0, 0x61+(index<<1), byte);
-
/* now, fill in DRBs where no physical slot exists */
for(i=index+1;i<4;i++) {
- pci_write_config8(ctrl->d0, 0x60+(i<<1),byte);
- pci_write_config8(ctrl->d0, 0x61+(i<<1),byte);
-
+ pci_write_config8(ctrl->d0, 0x40+i, byte);
}
return memsz;
}
-/* LAST_DRB_SLOT is a constant for any E7500 board */
-#define LAST_DRB_SLOT 0x67
+
+#define LAST_DRB_SLOT 0x43
static long spd_set_ram_size(const struct mem_controller *ctrl, long dimm_mask)
{
}
memsz = set_dimm_size(ctrl, sz, memsz, i);
}
+#if 0
/* For now hardset everything at 128MB boundaries */
/* %ebp has the ram size in multiples of 64MB */
-// cmpl $0, %ebp /* test if there is no mem - smbus went bad */
-// jz no_memory_bad_smbus
+/* cmpl $0, %ebp /* test if there is no mem - smbus went bad */*/
+/* jz no_memory_bad_smbus*/
if(memsz < 0x30) {
/* I should really adjust all of this in C after I have resources
* to all of the pcie devices.
pci_write_config16(ctrl->d0, 0xc8, word);
}
+#endif
return dimm_mask;
}
#if DEBUG_RAM_CONFIG
print_debug(spd_pre_init);
#endif
- //activate_spd_rom(ctrl);
+ /*activate_spd_rom(ctrl);*/
dimm_mask = spd_detect_dimms(ctrl);
if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
print_debug("No memory for this controller\n");
dimm_mask = spd_enable_clocks(ctrl, dimm_mask);
if (dimm_mask < 0)
goto hw_spd_err;
- //spd_verify_dimms(ctrl);
+ /*spd_verify_dimms(ctrl);*/
#if DEBUG_RAM_CONFIG
print_debug(spd_pre_set);
#endif
dimm_mask = spd_set_row_attributes(ctrl,dimm_mask);
+
if (dimm_mask < 0)
goto hw_spd_err;
dimm_mask = spd_set_dram_controller_mode(ctrl,dimm_mask);
+
if (dimm_mask < 0)
goto hw_spd_err;
+
+ /* skip for now until we just get "known good" up
dimm_mask = spd_set_cas_latency(ctrl,dimm_mask);
+ */
+
if (dimm_mask < 0)
goto hw_spd_err;
dimm_mask = spd_set_dram_timing(ctrl,dimm_mask);
if (dimm_mask < 0)
goto hw_spd_err;
+
#if DEBUG_RAM_CONFIG
print_debug(spd_post_init);
#endif
- //moved from dram_post_init
+ /*moved from dram_post_init*/
spd_set_ram_size(ctrl, dimm_mask);
- return;
+ dump_pci_device(PCI_DEV(0,0,1));
+ return;
+
hw_spd_err:
/* Unrecoverable error reading SPD data */
print_err("SPD error - reset\r\n");
}
- /* I have finally seen ram bad enough to cause LinuxBIOS
+ /* I have finally seen ram bad enough to cause coreboot
* to die in mysterious ways, before booting up far
* enough to run a memory tester. This code attempts
* to catch this blatantly bad ram, with a spot check.
* Only 64M of each side of each DIMM is currently mapped,
* so we can handle > 4GB of ram here.
*/
-#if 0
-#define bank_msg "Bank "
-#define side_msg " Side "
-static void verify_ram() {
- xorl %ecx, %ecx
- /* Check to see if the RAM is present,
- * in the specified bank and side.
- */
-1: movl %ecx, %ebx
- shrl $1, %ebx
- addl $((5<<8) | SMBUS_MEM_DEVICE_START), %ebx
- CALLSP(smbus_read_byte)
- jz 5f
- testl $1, %ecx
- jz 2f
- cmpb $2, %al
- jne 5f
-
- /* Display the bank and side we are spot checking.
- */
-2: CONSOLE_INFO_TX_STRING($bank_msg)
- movl %ecx, %ebx
- shrl $1, %ebx
- incl %ebx
- CONSOLE_INFO_TX_HEX8(%bl)
- CONSOLE_INFO_TX_STRING($side_msg)
- movl %ecx, %ebx
- andl $1, %ebx
- CONSOLE_INFO_TX_HEX8(%bl)
-
- /* Compute the memory address to spot check. */
- movl %ecx, %ebx
- xorl %eax, %eax
-3: testl %ebx, %ebx
- jz 4f
- addl $0x04000000, %eax
- decl %ebx
- jmp 3b
-4:
- /* Spot check 512K of RAM */
- movl %eax, %ebx
- addl $0x0007ffff, %ebx
- CALLSP(spot_check)
-5:
- /* Now find the next bank and side to spot check */
- incl %ecx
- cmpl $((SMBUS_MEM_DEVICE_END - SMBUS_MEM_DEVICE_START)<<1), %ecx
- jb 1b
- RET_LABEL(verify_ram)
-
-}
-#endif
-#if 0
static void ram_postinit(const struct mem_controller *ctrl) {
#if DEBUG_RAM_CONFIG
dumpnorth();
#endif
- /* Include a test to verify that memory is more or less working o.k.
- * This test is to catch programming errors and hardware that is out of
- * spec, not a test to see if the memory dimms are working 100%
- */
-//# CALL_LABEL(verify_ram)
- spd_set_ram_size(ctrl);
+ /*spd_set_ram_size(ctrl);*/
}
#define FIRST_NORMAL_REFERENCE() CALL_LABEL(ram_postinit)
#define SPECIAL_FINISHUP() CALL_LABEL(dram_finish)
-#endif
#define ecc_pre_init "Initializing ECC state...\r\n"
#define ecc_post_init "ECC state initialized.\r\n"
uint32_t dword;
uint8_t byte;
/* Test to see if ECC support is enabled */
- dword = pci_read_config32(ctrl->d0, 0x7c);
+ dword = pci_read_config32(ctrl->d0, 0x70);
dword >>=20;
- dword &=3;
- if(dword == 2) {
+ dword &=1;
+ if(dword == 1) {
#if DEBUG_RAM_CONFIG
- print_debug(ecc_pre_init);
+// print_debug(ecc_pre_init);
#endif
- /* Initialize ECC bits , use ECC zero mode (new to 7501)*/
- pci_write_config8(ctrl->d0, 0x52, 0x06);
- pci_write_config8(ctrl->d0, 0x52, 0x07);
- do {
- byte = pci_read_config8(ctrl->d0, 0x52);
-
- } while ( (byte & 0x08 ) == 0);
-
- pci_write_config8(ctrl->d0, 0x52, byte & 0xfc);
#if DEBUG_RAM_CONFIG
- print_debug(ecc_post_init);
+// print_debug(ecc_post_init);
#endif
-
- /* Clear the ECC error bits */
#if 0
- pci_write_config8(ctrl->d0f1, 0x80, 0x03); /* dev 0, function 1, offset 80 */
- pci_write_config8(ctrl->d0f1, 0x82, 0x03); /* dev 0, function 1, offset 82 */
-
- pci_write_config32(ctrl->d0f1, 0x40, 1<<18); /* clear dev 0, function 1, offset 40; bit 18 by writing a 1 to it */
- pci_write_config32(ctrl->d0f1, 0x44, 1<<18); /* clear dev 0, function 1, offset 44; bit 18 by writing a 1 to it */
-#endif
- pci_write_config8(ctrl->d0, 0x52, 0x0d);
- }
-
+ /* Clear the ECC error bits */
dword = pci_read_config32(ctrl->d0, 0x7c); /* FCS_EN */
dword |= (1<<17);
pci_write_config32(ctrl->d0, 0x7c, dword);
-
+#endif
+ }
#if DEBUG_RAM_CONFIG
- dumpnorth();
+// dumpnorth();
#endif
-// verify_ram();
+/* verify_ram(); */
}
-#if 0
-#define ERRFUNC(x, str) mem_err(x, str)
-
-
-ERRFUNC(invalid_dimm_type, "Invalid dimm type")
-ERRFUNC(spd_missing_data, "Missing sdram spd data")
-ERRFUNC(spd_invalid_data, "Invalid sdram spd data")
-ERRFUNC(spd_unsupported_data, "Unsupported sdram spd value")
-ERRFUNC(unsupported_page_size, "Unsupported page size")
-ERRFUNC(sdram_presence_mismatch, "DIMM presence mismatch")
-ERRFUNC(sdram_value_mismatch, "spd data does not match")
-ERRFUNC(unsupported_refresh_rate, "Unsuported spd refresh rate")
-ERRFUNC(inconsistent_cas_latencies, "No cas latency supported by all dimms")
-ERRFUNC(unsupported_rcd, "Unsupported ras to cas delay")
-#undef ERRFUNC
-
-#define mem_err_err "ERROR: "
-#define mem_err_pair " on dimm pair "
-#define mem_err_byte " spd byte "
-static void mem_err {
- movl %ebx, %edi
- CONSOLE_ERR_TX_STRING($mem_err_err)
- CONSOLE_ERR_TX_STRING(%esi)
- CONSOLE_ERR_TX_STRING($mem_err_pair)
- movl %edi, %ebx
- subb $(SMBUS_MEM_DEVICE_START), %bl
- CONSOLE_ERR_TX_HEX8(%bl)
- CONSOLE_ERR_TX_STRING($mem_err_byte)
- movl %edi, %ebx
- CONSOLE_ERR_TX_HEX8(%bh)
- jmp mem_stop
-
-}
-
-#endif
-
#if ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG
#define ram_enable_1 "Ram Enable 1\r\n"
/* Estimate that SLOW_DOWN_IO takes about 50&76us*/
/* delay for 200us */
+void udelay(int usecs)
+{
+ int i;
+ for(i = 0; i < usecs; i++)
+ outb(i&0xff, 0x80);
+}
-#define DO_DELAY \
+
+#if 0
+static void DO_DELAY(void){
udelay(200);
-// for(i=0; i<16;i++) { SLOW_DOWN_IO }
+}
+#endif
+
+#define DO_DELAY udelay(200);
+/*
+ for(i=0; i<16;i++) { SLOW_DOWN_IO }
+ */
#define EXTRA_DELAY DO_DELAY
int i;
uint32_t mchtst;
/* 1 & 2 Power up and start clocks */
- /* arg! the parts are memory mapped! For now, just grab address 0xc0000000 as the base, since I want to use
- * constants, not variables, for this.
+ /* let the games begin. More undocumented shit, so we'll just set it
+ * as intel sets it
*/
- mchtst = pci_read_config32(ctrl->d0, 0xf4);
- mchtst |= (1 << 22);
- pci_write_config32(ctrl->d0, 0xf4, mchtst);
-
+ mchtst = pci_read_config32(ctrl->d0, 0x68);
#if DEBUG_RAM_CONFIG
print_debug(ram_enable_1);
+ print_debug_hex32(mchtst);
+ dumpnorth();
+#endif
+ /*
+ mchtst = 0x10f10038;
+ pci_write_config32(ctrl->d0, 0x68, mchtst);
+ * can't find a ram power register ...
+ */
+
+#if DEBUG_RAM_CONFIG
+
print_debug(ram_enable_2);
#endif
/* 3. Apply NOP */
#if DEBUG_RAM_CONFIG
+ dump_pci_device(PCI_DEV(0, 0, 0)) ;
print_debug(ram_enable_3);
#endif
RAM_NOP(ctrl);
EXTRA_DELAY
-
+#undef DEBUG_RAM_CONFIG
+#define DEBUG_RAM_CONFIG 0
/* 4 Precharge all */
#if DEBUG_RAM_CONFIG
print_debug(ram_enable_4);
#endif
+#undef DEBUG_RAM_CONFIG
+#define DEBUG_RAM_CONFIG 0
RAM_PRECHARGE(ctrl);
EXTRA_DELAY
RAM_NORMAL(ctrl);
- // special from v1
- //FIRST_NORMAL_REFERENCE();
- //spd_set_ram_size(ctrl, 0x03);
+ /* special from v1*/
+ /*FIRST_NORMAL_REFERENCE();*/
+ /*spd_set_ram_size(ctrl, 0x03);*/
/* Finally enable refresh */
ENABLE_REFRESH(ctrl);
- //SPECIAL_FINISHUP();
+ /*SPECIAL_FINISHUP();*/
dram_finish(ctrl);
+ { char *c = (char *) 0;
+ *c = 'a';
+ print_debug("Test: ");
+ print_debug_hex8(*c);
+ print_debug("\r\n");
+ }
+
}
projects / coreboot.git / blobdiff