Rework i855GM/i855GME support

[coreboot.git] / src / northbridge / intel / i855 / northbridge.c

diff --git a/src/northbridge/intel/i855/northbridge.c b/src/northbridge/intel/i855/northbridge.c
index 77d1564672e4ebd4f01c7d429807c179bc3fd683..220f7220ce6d578069a49b6ba254fb63431940f1 100644 (file)
--- a/src/northbridge/intel/i855/northbridge.c
+++ b/src/northbridge/intel/i855/northbridge.c
@@ -25,6 +25,7 @@
 #include <stdint.h>
 #include <device/device.h>
 #include <device/pci.h>
+#include <device/pci_ids.h>
 #include <stdlib.h>
 #include <string.h>
 #include <bitops.h>
@@ -32,6 +33,26 @@
 #include <cpu/cpu.h>
 #include "chip.h"
 
+static void northbridge_init(device_t dev)
+{
+        printk(BIOS_SPEW, "Northbridge init\n");
+}
+
+static struct device_operations northbridge_operations = {
+        .read_resources = pci_dev_read_resources,
+        .set_resources = pci_dev_set_resources,
+        .enable_resources = pci_dev_enable_resources,
+        .init = northbridge_init,
+        .enable = 0,
+        .ops_pci = 0,
+};
+
+static const struct pci_driver northbridge_driver __pci_driver = {
+        .ops = &northbridge_operations,
+        .vendor = PCI_VENDOR_ID_INTEL,
+        .device = 0x3580,
+};
+
 static void ram_resource(device_t dev, unsigned long index,
         unsigned long basek, unsigned long sizek)
 {