/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2008 Joseph Smith <joe@smittys.pointclark.net>
+ * Copyright (C) 2008-2010 Joseph Smith <joe@settoplinux.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
#include <stdlib.h>
#include <string.h>
#include <bitops.h>
+#include <boot/tables.h>
#include "chip.h"
#include "i82830.h"
static void northbridge_init(device_t dev)
{
- printk_spew("Northbridge init\n");
+ printk(BIOS_SPEW, "Northbridge init\n");
}
static struct device_operations northbridge_operations = {
.ops_pci = 0,
};
-static struct pci_driver northbridge_driver __pci_driver = {
+static const struct pci_driver northbridge_driver __pci_driver = {
.ops = &northbridge_operations,
.vendor = PCI_VENDOR_ID_INTEL,
.device = 0x3575,
};
-static void ram_resource(device_t dev, unsigned long index,
- unsigned long basek, unsigned long sizek)
-{
- struct resource *resource;
-
- if (!sizek)
- return;
- resource = new_resource(dev, index);
- resource->base = ((resource_t) basek) << 10;
- resource->size = ((resource_t) sizek) << 10;
- resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE |
- IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
-}
+/* IGD memory */
+uint64_t uma_memory_base=0, uma_memory_size=0;
-static void tolm_test(void *gp, struct device *dev, struct resource *new)
+int add_northbridge_resources(struct lb_memory *mem)
{
- struct resource **best_p = gp;
- struct resource *best;
- best = *best_p;
- if (!best || (best->base > new->base))
- best = new;
- *best_p = best;
-}
+ printk(BIOS_DEBUG, "Adding IGD UMA memory area\n");
+ lb_add_memory_range(mem, LB_MEM_RESERVED,
+ uma_memory_base, uma_memory_size);
-static uint32_t find_pci_tolm(struct bus *bus)
-{
- struct resource *min;
- uint32_t tolm;
- min = 0;
- search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test,
- &min);
- tolm = 0xffffffffUL;
- if (min && tolm > min->base)
- tolm = min->base;
- return tolm;
+ return 0;
}
-#if CONFIG_HAVE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES==1
#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB
extern uint64_t high_tables_base, high_tables_size;
#endif
uint32_t pci_tolm;
int igd_memory = 0;
- pci_tolm = find_pci_tolm(&dev->link[0]);
- mc_dev = dev->link[0].children;
- if (mc_dev) {
- unsigned long tomk, tolmk;
- int idx;
-
- if (CONFIG_VIDEO_MB == 512) {
- igd_memory = (CONFIG_VIDEO_MB);
- } else {
- igd_memory = (CONFIG_VIDEO_MB * 1024);
- }
-
- /* Get the value of the highest DRB. This tells the end of
- * the physical memory. The units are ticks of 32MB
- * i.e. 1 means 32MB.
- */
- tomk = ((unsigned long)pci_read_config8(mc_dev, DRB + 3)) << 15;
- tomk -= igd_memory;
- printk_debug("Setting RAM size to %d\n", tomk);
-
- /* Compute the top of low memory. */
- tolmk = pci_tolm >> 10;
- if (tolmk >= tomk) {
- /* The PCI hole does does not overlap the memory. */
- tolmk = tomk;
- }
-
- /* Report the memory regions. */
- idx = 10;
- ram_resource(dev, idx++, 0, 640);
- ram_resource(dev, idx++, 1024, tolmk - 1024);
-
-#if CONFIG_HAVE_HIGH_TABLES==1
- /* Leave some space for ACPI, PIRQ and MP tables */
- high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024;
- high_tables_size = HIGH_TABLES_SIZE * 1024;
-#endif
+ pci_tolm = find_pci_tolm(dev->link_list);
+ mc_dev = dev->link_list->children;
+ if (!mc_dev)
+ return;
+
+ unsigned long tomk, tolmk;
+ int idx;
+
+ if (CONFIG_VIDEO_MB == 512) {
+ igd_memory = (CONFIG_VIDEO_MB);
+ printk(BIOS_DEBUG, "%dKB IGD UMA\n", igd_memory >> 10);
+ } else {
+ igd_memory = (CONFIG_VIDEO_MB * 1024);
+ printk(BIOS_DEBUG, "%dMB IGD UMA\n", igd_memory >> 10);
+ }
+
+ /* Get the value of the highest DRB. This tells the end of
+ * the physical memory. The units are ticks of 32MB
+ * i.e. 1 means 32MB.
+ */
+ tomk = ((unsigned long)pci_read_config8(mc_dev, DRB + 3)) << 15;
+ tomk -= igd_memory;
+
+ /* For reserving UMA memory in the memory map */
+ uma_memory_base = tomk * 1024ULL;
+ uma_memory_size = igd_memory * 1024ULL;
+ printk(BIOS_DEBUG, "Available memory: %ldKB\n", tomk);
+
+ /* Compute the top of low memory. */
+ tolmk = pci_tolm >> 10;
+ if (tolmk >= tomk) {
+ /* The PCI hole does does not overlap the memory. */
+ tolmk = tomk;
}
- assign_resources(&dev->link[0]);
+
+ /* Report the memory regions. */
+ idx = 10;
+ ram_resource(dev, idx++, 0, 640);
+ ram_resource(dev, idx++, 768, 256);
+ ram_resource(dev, idx++, 1024, tolmk - 1024);
+
+ assign_resources(dev->link_list);
+
+#if CONFIG_WRITE_HIGH_TABLES==1
+ /* Leave some space for ACPI, PIRQ and MP tables */
+ high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024;
+ high_tables_size = HIGH_TABLES_SIZE * 1024;
+#endif
}
static struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources,
- .enable_resources = enable_childrens_resources,
- .init = 0,
+ .enable_resources = NULL,
+ .init = NULL,
.scan_bus = pci_domain_scan_bus,
};
static void cpu_bus_init(device_t dev)
{
- initialize_cpus(&dev->link[0]);
+ initialize_cpus(dev->link_list);
}
static void cpu_bus_noop(device_t dev)
projects / coreboot.git / blobdiff