Please bear with me - another rename checkin. This qualifies as trivial, no

[coreboot.git] / src / northbridge / intel / i82810 / raminit.h

diff --git a/src/northbridge/intel/i82810/raminit.h b/src/northbridge/intel/i82810/raminit.h
index 43edd837d6d2232021067f8bcb7f76edf6c6445d..1e79397288820d2ec4ad7a1fc4a7a018ed2dffa3 100644 (file)
--- a/src/northbridge/intel/i82810/raminit.h
+++ b/src/northbridge/intel/i82810/raminit.h
@@ -1,5 +1,5 @@
 /*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
  *
  * Copyright (C) 2007 Corey Osgood <corey@slightlyhackish.com>
  *
@@ -21,7 +21,7 @@
 #ifndef NORTHBRIDGE_INTEL_I82810_RAMINIT_H
 #define NORTHBRIDGE_INTEL_I82810_RAMINIT_H
 
-/* The i810 supports max 2 dual-sided DIMMs. */
+/* The 82810 supports max. 2 dual-sided DIMMs. */
 #define DIMM_SOCKETS   2
 
 struct mem_controller {
@@ -29,9 +29,6 @@ struct mem_controller {
        uint16_t channel0[DIMM_SOCKETS];
 };
 
-
-#endif                         /* NORTHBRIDGE_INTEL_I82810_RAMINIT_H */
-
 /* The following table has been bumped over to this header to avoid clutter in 
  * raminit.c. It's used to translate the value read from SPD Byte 31 to a value
  * the northbridge can understand in DRP, aka Rx52[7:4], [3:0]. Where most
@@ -40,7 +37,7 @@ struct mem_controller {
  * this table is necessary.
  */
 
-/* TODO: Find a better way of doing this */
+/* TODO: Find a better way of doing this. */
 
 static const uint8_t translate_spd_to_i82810[] = {
        /* Note: 4MB sizes are not supported, so dual-sided DIMMs with a 4MB 
@@ -86,5 +83,7 @@ static const uint8_t translate_spd_to_i82810[] = {
        0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
        0xff, 0xff, 0xff, /* 0x31-3f    Invalid         */
        0x0f,   /*      0x40            256/0 or 256    */
-       /* Anything larger is not supported by the i810 */
+       /* Anything larger is not supported by the 82810. */
 };
+
+#endif                         /* NORTHBRIDGE_INTEL_I82810_RAMINIT_H */