/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2007-2008 Uwe Hermann <uwe@hermann-uwe.de>
+ * Copyright (C) 2007-2009 Uwe Hermann <uwe@hermann-uwe.de>
* Copyright (C) 2007 Corey Osgood <corey@slightlyhackish.com>
- * Copyright (C) 2008 Elia Yehuda <z4ziggy@gmail.com>
+ * Copyright (C) 2008-2009 Elia Yehuda <z4ziggy@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
*/
#include <spd.h>
-#include <sdram_mode.h>
#include <delay.h>
#include "i82810.h"
Macros and definitions.
-----------------------------------------------------------------------------*/
-/* Uncomment this to enable debugging output. */
-// #define DEBUG_RAM_SETUP 1
-
/* Debugging macros. */
-#if defined(DEBUG_RAM_SETUP)
+#define HAVE_ENOUGH_REGISTERS 0 /* Don't have enough registers to compile all
+ * debugging code with ROMCC
+ */
+#if CONFIG_DEBUG_RAM_SETUP
#define PRINT_DEBUG(x) print_debug(x)
#define PRINT_DEBUG_HEX8(x) print_debug_hex8(x)
#define PRINT_DEBUG_HEX16(x) print_debug_hex16(x)
#define PRINT_DEBUG_HEX32(x) print_debug_hex32(x)
-#define DUMPNORTH() dump_pci_device(PCI_DEV(0, 0, 0))
+// no dump_pci_device in src/northbridge/intel/i82810/
+// #define DUMPNORTH() dump_pci_device(PCI_DEV(0, 0, 0))
+#define DUMPNORTH()
#else
#define PRINT_DEBUG(x)
#define PRINT_DEBUG_HEX8(x)
/* MB */0, 0, 0, 8, 0, 16, 16, 0, 32, 32, 0, 64, 64, 0, 128, 128,
};
+struct dimm_info {
+ u8 ds; /* dual-sided */
+ u8 ss; /* single-sided */
+ u8 size;
+};
+
/*-----------------------------------------------------------------------------
SDRAM configuration functions.
-----------------------------------------------------------------------------*/
drp = (drp >> (i * 4)) & 0x0f;
dimm_size = translate_i82810_to_mb[drp];
- addr = (dimm_start * 1024 * 1024) + addr_offset;
if (dimm_size) {
+ addr = (dimm_start * 1024 * 1024) + addr_offset;
+#if HAVE_ENOUGH_REGISTERS
PRINT_DEBUG(" Sending RAM command 0x");
PRINT_DEBUG_HEX8(reg8);
PRINT_DEBUG(" to 0x");
PRINT_DEBUG_HEX32(addr);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
+#endif
read32(addr);
}
dimm_bank = translate_i82810_to_bank[drp];
- addr = ((dimm_start + dimm_bank) * 1024 * 1024) + addr_offset;
if (dimm_bank) {
+ addr = ((dimm_start + dimm_bank) * 1024 * 1024) + addr_offset;
+#if HAVE_ENOUGH_REGISTERS
PRINT_DEBUG(" Sending RAM command 0x");
PRINT_DEBUG_HEX8(reg8);
PRINT_DEBUG(" to 0x");
PRINT_DEBUG_HEX32(addr);
- PRINT_DEBUG("\r\n");
-
+ PRINT_DEBUG("\n");
+#endif
read32(addr);
}
if (smbus_read_byte(DIMM_SPD_BASE + i, 2) == 4) {
print_debug("Found DIMM in slot ");
print_debug_hex8(i);
- print_debug("\r\n");
+ print_debug("\n");
dimm_size = smbus_read_byte(DIMM_SPD_BASE + i, 31);
/* WISHLIST: would be nice to display it as decimal? */
print_debug("DIMM is 0x");
print_debug_hex8(dimm_size * 4);
- print_debug("MB\r\n");
+ print_debug("MB\n");
/* The i810 can't handle DIMMs larger than 128MB per
* side. This will fail if the DIMM uses a
*/
if (dimm_size > 32) {
print_err("DIMM row sizes larger than 128MB not"
- "supported on i810\r\n");
+ "supported on i810\n");
print_err
- ("Attempting to treat as 128MB DIMM\r\n");
+ ("Attempting to treat as 128MB DIMM\n");
dimm_size = 32;
}
print_debug("After translation, dimm_size is 0x");
print_debug_hex8(dimm_size);
- print_debug("\r\n");
+ print_debug("\n");
/* If the DIMM is dual-sided, the DRP value is +2 */
/* TODO: Figure out asymetrical configurations. */
if ((smbus_read_byte(DIMM_SPD_BASE + i, 127) | 0xf) ==
0xff) {
- print_debug("DIMM is dual-sided\r\n");
+ print_debug("DIMM is dual-sided\n");
dimm_size += 2;
}
} else {
print_debug("No DIMM found in slot ");
print_debug_hex8(i);
- print_debug("\r\n");
+ print_debug("\n");
/* If there's no DIMM in the slot, set value to 0. */
dimm_size = 0x00;
print_debug("DRP calculated to 0x");
print_debug_hex8(drp);
- print_debug("\r\n");
+ print_debug("\n");
pci_write_config8(PCI_DEV(0, 0, 0), DRP, drp);
}
* 0x1145 384MB 0xdf 256MB dual-sided 128MB single-sided
* 0x4445 384MB 0xfd 128MB single-sided 256MB dual-sided
* 0x0001 512MB 0xff 256MB dual-sided 256MB dual-sided
+ *
+ * See also:
+ * http://www.coreboot.org/pipermail/coreboot/2009-May/047966.html
*/
static void set_dram_buffer_strength(void)
{
- pci_write_config16(PCI_DEV(0, 0, 0), BUFF_SC, 0x77da);
+ struct dimm_info d0, d1;
+ u16 buff_sc;
+
+ /* Check first slot. */
+ d0.size = d0.ds = d0.ss = 0;
+ if (smbus_read_byte(DIMM_SPD_BASE, SPD_MEMORY_TYPE)
+ == SPD_MEMORY_TYPE_SDRAM) {
+ d0.size = smbus_read_byte(DIMM_SPD_BASE, SPD_BANK_DENSITY);
+ d0.ds = smbus_read_byte(DIMM_SPD_BASE, SPD_NUM_DIMM_BANKS) > 1;
+ d0.ss = !d0.ds;
+ }
+
+ /* Check second slot. */
+ d1.size = d1.ds = d1.ss = 0;
+ if (smbus_read_byte(DIMM_SPD_BASE + 1, SPD_MEMORY_TYPE)
+ == SPD_MEMORY_TYPE_SDRAM) {
+ d1.size = smbus_read_byte(DIMM_SPD_BASE + 1, SPD_BANK_DENSITY);
+ d1.ds = smbus_read_byte(DIMM_SPD_BASE + 1,
+ SPD_NUM_DIMM_BANKS) > 1;
+ d1.ss = !d1.ds;
+ }
+
+ buff_sc = 0;
+
+ /* Tame the beast... */
+ if ((d0.ds && d1.ds) || (d0.ds && d1.ss) || (d0.ss && d1.ds))
+ buff_sc |= 1;
+ if ((d0.size && !d1.size) || (!d0.size && d1.size) || (d0.ss && d1.ss))
+ buff_sc |= 1 << 1;
+ if ((d0.ds && !d1.size) || (!d0.size && d1.ds) || (d0.ss && d1.ss)
+ || (d0.ds && d1.ss) || (d0.ss && d1.ds))
+ buff_sc |= 1 << 2;
+ if ((d0.ss && !d1.size) || (!d0.size && d1.ss))
+ buff_sc |= 1 << 3;
+ if ((d0.size && !d1.size) || (!d0.size && d1.size))
+ buff_sc |= 1 << 4;
+ if ((d0.ds && !d1.size) || (!d0.size && d1.ds) || (d0.ds && d1.ss)
+ || (d0.ss && d1.ds))
+ buff_sc |= 1 << 6;
+ if ((d0.ss && !d1.size) || (!d0.size && d1.ss) || (d0.ss && d1.ss))
+ buff_sc |= 3 << 6;
+ if ((!d0.size && d1.ss) || (d0.ds && d1.ss) || (d0.ss && d1.ss))
+ buff_sc |= 1 << 8;
+ if (d0.size && !d1.size)
+ buff_sc |= 3 << 8;
+ if ((d0.ss && !d1.size) || (d0.ss && d1.ss) || (d0.ss && d1.ds))
+ buff_sc |= 1 << 10;
+ if (!d0.size && d1.size)
+ buff_sc |= 3 << 10;
+ if ((d0.size && !d1.size) || (d0.ss && !d1.size) || (!d0.size && d1.ss)
+ || (d0.ss && d1.ss) || (d0.ds && d1.ss))
+ buff_sc |= 1 << 12;
+ if (d0.size && !d1.size)
+ buff_sc |= 1 << 13;
+ if ((!d0.size && d1.size) || (d0.ss && !d1.size) || (d0.ss && d1.ss)
+ || (d0.ss && d1.ds))
+ buff_sc |= 1 << 14;
+ if (!d0.size && d1.size)
+ buff_sc |= 1 << 15;
+
+ print_debug("BUFF_SC calculated to 0x");
+ print_debug_hex16(buff_sc);
+ print_debug("\n");
+
+ pci_write_config16(PCI_DEV(0, 0, 0), BUFF_SC, buff_sc);
}
/*-----------------------------------------------------------------------------
static void sdram_set_registers(void)
{
- unsigned long val;
-
- /* TODO */
- pci_write_config8(PCI_DEV(0, 0, 0), GMCHCFG, 0x60);
-
- /* PAMR: Programmable Attributes Register
- * Every pair of bits controls an address range:
- * 00 = Disabled, all accesses are forwarded to the ICH
- * 01 = Read Only
- * 10 = Write Only
- * 11 = Read/Write
-
- * Bit Range
- * 7:6 000F0000 - 000FFFFF
- * 5:4 000E0000 - 000EFFFF
- * 3:2 000D0000 - 000DFFFF
- * 1:0 000C0000 - 000CFFFF
- */
+ u8 reg8;
+ u16 reg16, did;
+
+ did = pci_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID);
/* Ideally, this should be R/W for as many ranges as possible. */
- pci_write_config8(PCI_DEV(0, 0, 0), PAM, 0xff);
-
- /* Enabling the VGA Framebuffer currently screws up the rest of the boot.
- * Disable for now */
-
- /* Enable 1MB framebuffer. */
- //pci_write_config8(PCI_DEV(0, 0, 0), SMRAM, 0xC0);
-
- //val = pci_read_config16(PCI_DEV(0, 0, 0), MISSC);
- /* Preserve reserved bits. */
- //val &= 0xff06;
- /* Set graphics cache window to 32MB, no power throttling. */
- //val |= 0x0001;
- //pci_write_config16(PCI_DEV(0, 0, 0), MISSC, val);
-
- //val = pci_read_config8(PCI_DEV(0, 0, 0), MISSC2);
- /* Enable graphics palettes and clock gating (not optional!) */
- //val |= 0x06;
- //pci_write_config8(PCI_DEV(0, 0, 0), MISSC2, val);
+ pci_write_config8(PCI_DEV(0, 0, 0), PAMR, 0xff);
+
+ /* Set size for onboard-VGA framebuffer. */
+ reg8 = pci_read_config8(PCI_DEV(0, 0, 0), SMRAM);
+ reg8 &= 0x3f; /* Disable graphics (for now). */
+#if CONFIG_VIDEO_MB
+ if (CONFIG_VIDEO_MB == 512)
+ reg8 |= (1 << 7); /* Enable graphics (512KB RAM). */
+ else if (CONFIG_VIDEO_MB == 1)
+ reg8 |= (1 << 7) | (1 << 6); /* Enable graphics (1MB RAM). */
+#endif
+ pci_write_config8(PCI_DEV(0, 0, 0), SMRAM, reg8);
+
+ /* MISSC2: Bits 1, 2, 6, 7 must be set for VGA (see datasheet). */
+ reg8 = pci_read_config8(PCI_DEV(0, 0, 0), MISSC2);
+ reg8 |= (1 << 1); /* Instruction Parser Unit-Level Clock Gating */
+ reg8 |= (1 << 2); /* Palette Load Select */
+ if (did == 0x7124) {
+ /* Bits 6 and 7 are only available on 82810E (not 82810). */
+ reg8 |= (1 << 6); /* Text Immediate Blit */
+ reg8 |= (1 << 7); /* Must be 1 as per datasheet. */
+ }
+ pci_write_config8(PCI_DEV(0, 0, 0), MISSC2, reg8);
}
static void sdram_set_spd_registers(void)
int i;
/* 1. Apply NOP. */
- PRINT_DEBUG("RAM Enable 1: Apply NOP\r\n");
+ PRINT_DEBUG("RAM Enable 1: Apply NOP\n");
do_ram_command(RAM_COMMAND_NOP);
udelay(200);
/* 2. Precharge all. Wait tRP. */
- PRINT_DEBUG("RAM Enable 2: Precharge all\r\n");
+ PRINT_DEBUG("RAM Enable 2: Precharge all\n");
do_ram_command(RAM_COMMAND_PRECHARGE);
udelay(1);
/* 3. Perform 8 refresh cycles. Wait tRC each time. */
- PRINT_DEBUG("RAM Enable 3: CBR\r\n");
+ PRINT_DEBUG("RAM Enable 3: CBR\n");
for (i = 0; i < 8; i++) {
do_ram_command(RAM_COMMAND_CBR);
udelay(1);
}
/* 4. Mode register set. Wait two memory cycles. */
- PRINT_DEBUG("RAM Enable 4: Mode register set\r\n");
+ PRINT_DEBUG("RAM Enable 4: Mode register set\n");
do_ram_command(RAM_COMMAND_MRS);
udelay(2);
- /* 5. Normal operation (enables refresh) */
- PRINT_DEBUG("RAM Enable 5: Normal operation\r\n");
+ /* 5. Normal operation (enables refresh at 15.6usec). */
+ PRINT_DEBUG("RAM Enable 5: Normal operation\n");
do_ram_command(RAM_COMMAND_NORMAL);
udelay(1);
- PRINT_DEBUG("Northbridge following SDRAM init:\r\n");
+ PRINT_DEBUG("Northbridge following SDRAM init:\n");
DUMPNORTH();
}
projects / coreboot.git / blobdiff