Move C labels to start-of-line

[coreboot.git] / src / northbridge / intel / e7525 / raminit.c

diff --git a/src/northbridge/intel/e7525/raminit.c b/src/northbridge/intel/e7525/raminit.c
index be44434bf58ab7d8267b6fa99596e6352cc9be60..b5895bc64743114824c55fe64e122b53b5257eb6 100644 (file)
--- a/src/northbridge/intel/e7525/raminit.c
+++ b/src/northbridge/intel/e7525/raminit.c
@@ -23,6 +23,10 @@
 #include <stdlib.h>
 #include "raminit.h"
 #include "e7525.h"
+#include <pc80/mc146818rtc.h>
+#if CONFIG_HAVE_OPTION_TABLE
+#include "option_table.h"
+#endif
 
 #define BAR 0x40000000
 
@@ -160,7 +164,7 @@ static struct dimm_size spd_get_dimm_size(unsigned device)
 hw_err:
        sz.side1 = 0;
        sz.side2 = 0;
- out:
+out:
        return sz;
 
 }
@@ -287,7 +291,7 @@ static int spd_set_row_attributes(const struct mem_controller *ctrl,
        /* If an hw_error occurs report that I have no memory */
 hw_err:
        dra = 0;
- out:
+out:
        return dra;
 
 }
@@ -619,11 +623,13 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
 
        }
        ecc = 2;
-       if (read_option(CMOS_VSTART_ECC_memory,CMOS_VLEN_ECC_memory,1) == 0) {
+#if CONFIG_HAVE_OPTION_TABLE
+       if (read_option(ECC_memory, 1) == 0) {
                ecc = 0;  /* ECC off in CMOS so disable it */
                print_debug("ECC off\n");
-       }
-       else {
+       } else
+#endif
+       {
                print_debug("ECC on\n");
        }
        drc &= ~(3 << 20); /* clear the ecc bits */
@@ -658,7 +664,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
        /* If an hw_error occurs report that I have no memory */
 hw_err:
        drc = 0;
- out:
+out:
        return drc;
 }
 
@@ -1049,12 +1055,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
        print_debug("Starting SDRAM Enable\n");
 
        /* 0x80 */
-#ifdef DIMM_MAP_LOGICAL
        pci_write_config32(ctrl->f0, DRM,
-               0x00210000 | DIMM_MAP_LOGICAL);
-#else
-       pci_write_config32(ctrl->f0, DRM, 0x00211248);
-#endif
+               0x00210000 | CONFIG_DIMM_MAP_LOGICAL);
        /* set dram type and Front Side Bus freq. */
        drc = spd_set_dram_controller_mode(ctrl, mask);
        if( drc == 0) {
@@ -1102,9 +1104,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 
                write32(BAR+0x100, (0x83000000 | (i<<20)));
 
-               data32 = read32(BAR+DCALCSR);
-               while(data32 & 0x80000000)
-                       data32 = read32(BAR+DCALCSR);
+               do data32 = read32(BAR+DCALCSR);
+               while(data32 & 0x80000000);
 
        }
 
@@ -1113,9 +1114,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 
        for(cs=0;cs<8;cs++) {
                write32(BAR + DCALCSR, (0x83000000 | (cs<<20)));
-               data32 = read32(BAR+DCALCSR);
-               while(data32 & 0x80000000)
-                       data32 = read32(BAR+DCALCSR);
+               do data32 = read32(BAR+DCALCSR);
+               while(data32 & 0x80000000);
        }
 
        /* Precharg all banks */
@@ -1126,9 +1126,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
                 else   /* DDR1  */
                         write32(BAR+DCALADDR, 0x00000000);
                write32(BAR+DCALCSR, (0x83000002 | (cs<<20)));
-               data32 = read32(BAR+DCALCSR);
-               while(data32 & 0x80000000)
-                       data32 = read32(BAR+DCALCSR);
+               do data32 = read32(BAR+DCALCSR);
+               while(data32 & 0x80000000);
        }
 
        /* EMRS dll's enabled */
@@ -1140,9 +1139,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
                 else   /* DDR1  */
                         write32(BAR+DCALADDR, 0x00000001);
                write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
-               data32 = read32(BAR+DCALCSR);
-               while(data32 & 0x80000000)
-                       data32 = read32(BAR+DCALCSR);
+               do data32 = read32(BAR+DCALCSR);
+               while(data32 & 0x80000000);
        }
        /* MRS reset dll's */
        do_delay();
@@ -1161,9 +1159,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
        for(cs=0;cs<8;cs++) {
                write32(BAR+DCALADDR, mode_reg);
                write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
-               data32 = read32(BAR+DCALCSR);
-               while(data32 & 0x80000000)
-                       data32 = read32(BAR+DCALCSR);
+               do data32 = read32(BAR+DCALCSR);
+               while(data32 & 0x80000000);
        }
 
        /* Precharg all banks */
@@ -1176,25 +1173,22 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
                 else   /* DDR1  */
                         write32(BAR+DCALADDR, 0x00000000);
                write32(BAR+DCALCSR, (0x83000002 | (cs<<20)));
-               data32 = read32(BAR+DCALCSR);
-               while(data32 & 0x80000000)
-                       data32 = read32(BAR+DCALCSR);
+               do data32 = read32(BAR+DCALCSR);
+               while(data32 & 0x80000000);
        }
 
        /* Do 2 refreshes */
        do_delay();
        for(cs=0;cs<8;cs++) {
                write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
-               data32 = read32(BAR+DCALCSR);
-               while(data32 & 0x80000000)
-                       data32 = read32(BAR+DCALCSR);
+               do data32 = read32(BAR+DCALCSR);
+               while(data32 & 0x80000000);
        }
        do_delay();
        for(cs=0;cs<8;cs++) {
                write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
-               data32 = read32(BAR+DCALCSR);
-               while(data32 & 0x80000000)
-                       data32 = read32(BAR+DCALCSR);
+               do data32 = read32(BAR+DCALCSR);
+               while(data32 & 0x80000000);
        }
        do_delay();
        /* for good luck do 6 more */
@@ -1227,9 +1221,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
        for(cs=0;cs<8;cs++) {
                write32(BAR+DCALADDR, (mode_reg & ~(1<<24)));
                write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
-               data32 = read32(BAR+DCALCSR);
-               while(data32 & 0x80000000)
-                       data32 = read32(BAR+DCALCSR);
+               do data32 = read32(BAR+DCALCSR);
+               while(data32 & 0x80000000);
        }
 
        /* Do only if DDR2  EMRS dll's enabled */
@@ -1238,9 +1231,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
                 for(cs=0;cs<8;cs++) {
                         write32(BAR+DCALADDR, (0x0b940001));
                         write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
-                       data32 = read32(BAR+DCALCSR);
-                       while(data32 & 0x80000000)
-                               data32 = read32(BAR+DCALCSR);
+                       do data32 = read32(BAR+DCALCSR);
+                       while(data32 & 0x80000000);
                 }
         }
 
@@ -1281,9 +1273,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 
        for(cs=0;cs<8;cs++) {
                write32(BAR+DCALCSR, (0x830831d8 | (cs<<20)));
-               data32 = read32(BAR+DCALCSR);
-               while(data32 & 0x80000000)
-                       data32 = read32(BAR+DCALCSR);
+               do data32 = read32(BAR+DCALCSR);
+               while(data32 & 0x80000000);
        }
 
        /* Bring memory subsystem on line */