Same conversion as with resources from static arrays to lists, except

[coreboot.git] / src / northbridge / intel / e7520 / northbridge.c

diff --git a/src/northbridge/intel/e7520/northbridge.c b/src/northbridge/intel/e7520/northbridge.c
index f2b2a0f3a0f2ba42613d484ddaa65eccd2e88ed6..c0580bbe3e71233978bfea74c81af57e6d9627bf 100644 (file)
--- a/src/northbridge/intel/e7520/northbridge.c
+++ b/src/northbridge/intel/e7520/northbridge.c
@@ -16,7 +16,7 @@
 
 static unsigned int max_bus;
 
-static void ram_resource(device_t dev, unsigned long index, 
+static void ram_resource(device_t dev, unsigned long index,
        unsigned long basek, unsigned long sizek)
 {
        struct resource *resource;
@@ -28,30 +28,6 @@ static void ram_resource(device_t dev, unsigned long index,
                IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
 }
 
-
-static void pci_domain_read_resources(device_t dev)
-{
-       struct resource *resource;
-
-       /* Initialize the system wide io space constraints */
-       resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
-       resource->base  = 0;
-       resource->size  = 0;
-       resource->align = 0;
-       resource->gran  = 0;
-       resource->limit = 0xffffUL;
-       resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-
-       /* Initialize the system wide memory resources constraints */
-       resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
-       resource->base  = 0;
-       resource->size  = 0;
-       resource->align = 0;
-       resource->gran  = 0;
-       resource->limit = 0xffffffffUL;
-       resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-}
-
 static void tolm_test(void *gp, struct device *dev, struct resource *new)
 {
        struct resource **best_p = gp;
@@ -76,7 +52,7 @@ static uint32_t find_pci_tolm(struct bus *bus)
        return tolm;
 }
 
-#if HAVE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES==1
 #define HIGH_TABLES_SIZE 64    // maximum size of high tables in KB
 extern uint64_t high_tables_base, high_tables_size;
 #endif
@@ -86,17 +62,17 @@ static void pci_domain_set_resources(device_t dev)
        device_t mc_dev;
        uint32_t pci_tolm;
 
-        pci_tolm = find_pci_tolm(&dev->link[0]);
+        pci_tolm = find_pci_tolm(dev->link_list);
 
 #if 1
-       printk_debug("PCI mem marker = %x\n", pci_tolm);
-#endif 
+       printk(BIOS_DEBUG, "PCI mem marker = %x\n", pci_tolm);
+#endif
        /* FIXME Me temporary hack */
        if(pci_tolm > 0xe0000000)
                pci_tolm = 0xe0000000;
        /* Ensure pci_tolm is 128M aligned */
        pci_tolm &= 0xf8000000;
-       mc_dev = dev->link[0].children;
+       mc_dev = dev->link_list->children;
        if (mc_dev) {
                /* Figure out which areas are/should be occupied by RAM.
                 * This is all computed in kilobytes and converted to/from
@@ -122,7 +98,7 @@ static void pci_domain_set_resources(device_t dev)
                        remapbasek   = 0x3ff << 16;
                        remaplimitk  = 0 << 16;
                        remapoffsetk = 0 << 16;
-               } 
+               }
                else {
                        /* The PCI memory hole overlaps memory
                         * setup the remap window.
@@ -165,26 +141,23 @@ static void pci_domain_set_resources(device_t dev)
                        ram_resource(dev, 5, 4096*1024, tomk - 4*1024*1024);
                }
                if (remaplimitk >= remapbasek) {
-                       ram_resource(dev, 6, remapbasek, 
+                       ram_resource(dev, 6, remapbasek,
                                (remaplimitk + 64*1024) - remapbasek);
                }
 
-#if HAVE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES==1
                /* Leave some space for ACPI, PIRQ and MP tables */
                high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024;
                high_tables_size = HIGH_TABLES_SIZE * 1024;
 #endif
        }
-       assign_resources(&dev->link[0]);
+       assign_resources(dev->link_list);
 }
 
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
+static u32 e7520_domain_scan_bus(device_t dev, u32 max)
 {
-       max = pci_scan_bus(&dev->link[0], 0, 0xff, max);
-       if (max > max_bus) {
-               max_bus = max;
-       }
-       return max;
+       max_bus = pci_domain_scan_bus(dev, max);
+       return max_bus;
 }
 
 static struct device_operations pci_domain_ops = {
@@ -192,7 +165,7 @@ static struct device_operations pci_domain_ops = {
        .set_resources    = pci_domain_set_resources,
        .enable_resources = enable_childrens_resources,
        .init             = 0,
-       .scan_bus         = pci_domain_scan_bus,
+       .scan_bus         = e7520_domain_scan_bus,
        .ops_pci_bus      = &pci_cf8_conf1, /* Do we want to use the memory mapped space here? */
 };
 
@@ -210,9 +183,8 @@ static void mc_read_resources(device_t dev)
 
 static void mc_set_resources(device_t dev)
 {
-       struct resource *resource, *last;
+       struct resource *resource;
 
-       last = &dev->resource[dev->resources];
        resource = find_resource(dev, 0xcf);
        if (resource) {
                report_resource_stored(dev, resource, "<mmconfig>");
@@ -222,7 +194,7 @@ static void mc_set_resources(device_t dev)
 
 static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {
-       pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, 
+       pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
                ((device & 0xffff) << 16) | (vendor & 0xffff));
 }
 
@@ -247,7 +219,7 @@ static const struct pci_driver mc_driver __pci_driver = {
 
 static void cpu_bus_init(device_t dev)
 {
-        initialize_cpus(&dev->link[0]);
+        initialize_cpus(dev->link_list);
 }
 
 static void cpu_bus_noop(device_t dev)