/* This was originally for the e7500, modified for e7501
- * The primary differences are that 7501 apparently can
+ * The primary differences are that 7501 apparently can
* support single channel RAM (i haven't tested),
* CAS1.5 is no longer supported, The ECC scrubber
* now supports a mode to zero RAM and init ECC in one step
- * and the undocumented registers at 0x80 require new
+ * and the undocumented registers at 0x80 require new
* (undocumented) values determined by guesswork and
* comparison w/ OEM BIOS values.
* Steven James 02/06/2003
#include <stdlib.h>
#include "e7501.h"
-// Uncomment this to enable run-time checking of DIMM parameters
+/*-----------------------------------------------------------------------------
+Definitions:
+-----------------------------------------------------------------------------*/
+
+// Uncomment this to enable run-time checking of DIMM parameters
// for dual-channel operation
// Unfortunately the code seems to chew up several K of space.
//#define VALIDATE_DIMM_COMPATIBILITY
unsigned long side2;
};
-/*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
-/* DEFINITIONS */
-/**********************************************************************************/
-
static const uint32_t refresh_frequency[] = {
- /* Relative frequency (array value) of each E7501 Refresh Mode Select
+ /* Relative frequency (array value) of each E7501 Refresh Mode Select
* (RMS) value (array index)
* 0 == least frequent refresh (longest interval between refreshes)
- * [0] disabled -> 0
+ * [0] disabled -> 0
* [1] 15.6 usec -> 2
* [2] 7.8 usec -> 3
* [3] 64 usec -> 1
};
static const uint32_t refresh_rate_map[] = {
- /* Map the JEDEC spd refresh rates (array index) to E7501 Refresh Mode
+ /* Map the JEDEC spd refresh rates (array index) to E7501 Refresh Mode
* Select values (array value)
* These are all the rates defined by JESD21-C Appendix D, Rev. 1.0
- * The E7501 supports only 15.6 us (1), 7.8 us (2), 64 us (3), and
+ * The E7501 supports only 15.6 us (1), 7.8 us (2), 64 us (3), and
* 64 clock (481 ns) (7) refresh.
* [0] == 15.625 us -> 15.6 us
* [1] == 3.9 us -> 481 ns
*/
// Not everyone wants to be Super Micro Computer, Inc.
// The mainboard should set this if desired.
- // 0x2c, 0, (0x15d9 << 0) | (0x3580 << 16),
+ // 0x2c, 0, (0x15d9 << 0) | (0x3580 << 16),
/* Undocumented
* (DRAM Read Timing Control, if similar to 855PM?)
* CAS 2.0 values taken from Intel BIOS settings, others are a guess
* and may be terribly wrong. Old values preserved as comments until I
* figure this out for sure.
- * e7501 docs claim that CAS1.5 is unsupported, so it may or may not
+ * e7501 docs claim that CAS1.5 is unsupported, so it may or may not
* work at all.
* Steven James 02/06/2003
*/
- /* NOTE: values now configured in configure_e7501_cas_latency() based
+ /* NOTE: values now configured in configure_e7501_cas_latency() based
* on SPD info and total number of DIMMs (per Intel)
*/
/* DRB - DRAM Row Boundary Registers
* 0x60 - 0x6F
* An array of 8 byte registers, which hold the ending
- * memory address assigned to each pair of DIMMS, in 64MB
- * granularity.
+ * memory address assigned to each pair of DIMMS, in 64MB
+ * granularity.
*/
// Conservatively say each row has 64MB of ram, we will fix this up later
// NOTE: These defaults allow us to prime all of the DIMMs on the board
0x60, 0x00000000, (0x01 << 0) | (0x02 << 8) | (0x03 << 16) | (0x04 << 24),
0x64, 0x00000000, (0x05 << 0) | (0x06 << 8) | (0x07 << 16) | (0x08 << 24),
- /* DRA - DRAM Row Attribute Register
+ /* DRA - DRAM Row Attribute Register
* 0x70 Row 0,1
* 0x71 Row 2,3
* 0x72 Row 4,5
// .long 0x7c, 0xff8cfcff, (1<<22)|(2 << 20)|(1 << 17)|(1 << 16)| (0 << 8),
// .long 0x7c, 0xff80fcff, (1<<22)|(2 << 20)|(1 << 18)|(1 << 17)|(1 << 16)| (0 << 8),
- // Default to dual-channel mode, ECC, 1-clock address/cmd hold
+ // Default to dual-channel mode, ECC, 1-clock address/cmd hold
// NOTE: configure_e7501_dram_controller_mode() configures further
0x7c, 0xff8ef8ff, (1 << 22) | (2 << 20) | (1 << 16) | (0 << 8),
0xf4, 0x3f8ffffd, 0x40300002,
#ifdef SUSPICIOUS_LOOKING_CODE
- // SJM: Undocumented.
+ // SJM: Undocumented.
// This will access D2:F0:0x50, is this correct??
0x1050, 0xffffffcf, 0x00000030,
#endif
0x88888888, 0x88888888, 0x88888888, 0x88888888,
};
-/*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
-/* TABLES */
-/**********************************************************************************/
+/*-----------------------------------------------------------------------------
+Delay functions:
+-----------------------------------------------------------------------------*/
+
#define SLOW_DOWN_IO inb(0x80)
//#define SLOW_DOWN_IO udelay(40);
#define EXTRA_DELAY DO_DELAY
-/*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
-/* DELAY FUNCTIONS */
-/**********************************************************************************/
-
static void die_on_spd_error(int spd_return_value)
{
if (spd_return_value < 0)
die("Error reading SPD info\n");
}
-//----------------------------------------------------------------------------------
-// Function: sdram_spd_get_page_size
-// Parameters: dimm_socket_address - SMBus address of DIMM socket to interrogate
-// Return Value: struct dimm_size - log2(page size) for each side of the DIMM.
-// Description: Calculate the page size for each physical bank of the DIMM:
-// log2(page size) = (# columns) + log2(data width)
-//
-// NOTE: page size is the total number of data bits in a row.
-//
-static struct dimm_size sdram_spd_get_page_size(uint16_t
- dimm_socket_address)
+/*-----------------------------------------------------------------------------
+Serial presence detect (SPD) functions:
+-----------------------------------------------------------------------------*/
+
+/**
+ * Calculate the page size for each physical bank of the DIMM:
+ * log2(page size) = (# columns) + log2(data width)
+ *
+ * NOTE: Page size is the total number of data bits in a row.
+ *
+ * @param dimm_socket_address SMBus address of DIMM socket to interrogate.
+ * @return log2(page size) for each side of the DIMM.
+ */
+static struct dimm_size sdram_spd_get_page_size(uint16_t dimm_socket_address)
{
uint16_t module_data_width;
int value;
return pgsz; // Never reached
}
-//----------------------------------------------------------------------------------
-// Function: sdram_spd_get_width
-// Parameters: dimm_socket_address - SMBus address of DIMM socket to interrogate
-// Return Value: dimm_size - width in bits of each DIMM side's DRAMs.
-// Description: Read the width in bits of each DIMM side's DRAMs via SPD.
-// (i.e. 4, 8, 16)
-//
+/**
+ * Read the width in bits of each DIMM side's DRAMs via SPD (i.e. 4, 8, 16).
+ *
+ * @param dimm_socket_address SMBus address of DIMM socket to interrogate.
+ * @return Width in bits of each DIMM side's DRAMs.
+ */
static struct dimm_size sdram_spd_get_width(uint16_t dimm_socket_address)
{
int value;
return width;
}
-//----------------------------------------------------------------------------------
-// Function: spd_get_dimm_size
-// Parameters: dimm_socket_address - SMBus address of DIMM socket to interrogate
-// Return Value: dimm_size - log2(number of bits) for each side of the DIMM
-// Description: Calculate the log base 2 size in bits of both DIMM sides.
-// log2(# bits) = (# columns) + log2(data width) +
-// (# rows) + log2(banks per SDRAM)
-//
-// Note that it might be easier to use SPD byte 31 here, it has the
-// DIMM size as a multiple of 4MB. The way we do it now we can size
-// both sides of an asymmetric dimm.
-//
+/**
+ * Calculate the log base 2 size in bits of both DIMM sides.
+ *
+ * log2(# bits) = (# columns) + log2(data width) +
+ * (# rows) + log2(banks per SDRAM)
+ *
+ * Note that it might be easier to use SPD byte 31 here, it has the DIMM size
+ * as a multiple of 4MB. The way we do it now we can size both sides of an
+ * asymmetric DIMM.
+ *
+ * @param dimm_socket_address SMBus address of DIMM socket to interrogate.
+ * @return log2(number of bits) for each side of the DIMM.
+ */
static struct dimm_size spd_get_dimm_size(unsigned dimm_socket_address)
{
int value;
}
#ifdef VALIDATE_DIMM_COMPATIBILITY
-//----------------------------------------------------------------------------------
-// Function: are_spd_values_equal
-// Parameters: spd_byte_number -
-// dimmN_address - SMBus addresses of DIMM sockets to interrogate
-// Return Value: 1 if both DIMM sockets report the same value for the specified
-// SPD parameter; 0 if the values differed or an error occurred.
-// Description: Determine whether two DIMMs have the same value for a SPD parameter.
-//
+
+/**
+ * Determine whether two DIMMs have the same value for an SPD parameter.
+ *
+ * @param spd_byte_number The SPD byte number to compare in both DIMMs.
+ * @param dimm0_address SMBus address of the 1st DIMM socket to interrogate.
+ * @param dimm1_address SMBus address of the 2nd DIMM socket to interrogate.
+ * @return 1 if both DIMM sockets report the same value for the specified
+ * SPD parameter, 0 if the values differed or an error occurred.
+ */
static uint8_t are_spd_values_equal(uint8_t spd_byte_number,
uint16_t dimm0_address,
uint16_t dimm1_address)
{
uint8_t bEqual = 0;
-
int dimm0_value = spd_read_byte(dimm0_address, spd_byte_number);
int dimm1_value = spd_read_byte(dimm1_address, spd_byte_number);
}
#endif
-//----------------------------------------------------------------------------------
-// Function: spd_get_supported_dimms
-// Parameters: ctrl - PCI addresses of memory controller functions, and
-// SMBus addresses of DIMM slots on the mainboard
-// Return Value: uint8_t - a bitmask indicating which of the possible sockets
-// for each channel was found to contain a compatible DIMM.
-// Bit 0 corresponds to the closest socket for channel 0,
-// Bit 1 to the next socket for channel 0,
-// ...
-// Bit MAX_DIMM_SOCKETS_PER_CHANNEL-1 to the last socket for channel 0,
-// Bit MAX_DIMM_SOCKETS_PER_CHANNEL is the closest socket for channel 1,
-// ...
-// Bit 2*MAX_DIMM_SOCKETS_PER_CHANNEL-1 is the last socket for channel 1
-// Description: Scan for compatible DIMMs.
-// The code in this module only supports dual-channel operation,
-// so we test that compatible DIMMs are paired.
-//
+/**
+ * Scan for compatible DIMMs.
+ *
+ * The code in this module only supports dual-channel operation, so we test
+ * that compatible DIMMs are paired.
+ *
+ * @param ctrl PCI addresses of memory controller functions, and SMBus
+ * addresses of DIMM slots on the mainboard.
+ * @return A bitmask indicating which of the possible sockets for each channel
+ * was found to contain a compatible DIMM.
+ * Bit 0 corresponds to the closest socket for channel 0
+ * Bit 1 to the next socket for channel 0
+ * ...
+ * Bit MAX_DIMM_SOCKETS_PER_CHANNEL-1 to the last socket for channel 0
+ * Bit MAX_DIMM_SOCKETS_PER_CHANNEL is the closest socket for channel 1
+ * ...
+ * Bit 2*MAX_DIMM_SOCKETS_PER_CHANNEL-1 is the last socket for channel 1
+ */
static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl)
{
int i;
return dimm_mask;
}
-/*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
-/* SPD (SERIAL PRESENCE DETECT) FUNCTIONS */
-/**********************************************************************************/
-
-//----------------------------------------------------------------------------------
-// Function: do_ram_command
-// Parameters:
-// command - specifies the command to be sent to the DIMMs:
-// RAM_COMMAND_NOP - No Operation
-// RAM_COMMAND_PRECHARGE - Precharge all banks
-// RAM_COMMAND_MRS - Load Mode Register
-// RAM_COMMAND_EMRS - Load Extended Mode Register
-// RAM_COMMAND_CBR - Auto Refresh ("CAS-before-RAS")
-// RAM_COMMAND_NORMAL - Normal operation
-// jedec_mode_bits - for mode register set & extended mode register set
-// commands, bits 0-12 contain the register value in JEDEC format.
-// Return Value: None
-// Description: Send the specified command to all DIMMs.
-//
+/*-----------------------------------------------------------------------------
+SDRAM configuration functions:
+-----------------------------------------------------------------------------*/
+
+/**
+ * Send the specified command to all DIMMs.
+ *
+ * @param command Specifies the command to be sent to the DIMMs.
+ * @param jedec_mode_bits For the MRS & EMRS commands, bits 0-12 contain the
+ * register value in JEDEC format.
+ */
static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits)
{
int i;
dram_controller_mode |= command;
pci_write_config32(PCI_DEV(0, 0, 0), DRC, dram_controller_mode);
- // RAM_COMMAND_NORMAL is an exception.
+ // RAM_COMMAND_NORMAL is an exception.
// It affects only the memory controller and does not need to be "sent" to the DIMMs.
if (command != RAM_COMMAND_NORMAL) {
// NOTE: 0x40 * 64 MB == 4 GB
ASSERT(dimm_start_64M_multiple < 0x40);
- // NOTE: 2^26 == 64 MB
+ // NOTE: 2^26 == 64 MB
uint32_t dimm_start_address =
dimm_start_64M_multiple << 26;
}
}
-//----------------------------------------------------------------------------------
-// Function: set_ram_mode
-// Parameters: jedec_mode_bits - for mode register set & extended mode register set
-// commands, bits 0-12 contain the register value in JEDEC format.
-// Return Value: None
-// Description: Set the mode register of all DIMMs. The proper CAS# latency
-// setting is added to the mode bits specified by the caller.
-//
+/**
+ * Set the mode register of all DIMMs.
+ *
+ * The proper CAS# latency setting is added to the mode bits specified
+ * by the caller.
+ *
+ * @param jedec_mode_bits For the MRS & EMRS commands, bits 0-12 contain the
+ * register value in JEDEC format.
+ */
static void set_ram_mode(uint16_t jedec_mode_bits)
{
ASSERT(!(jedec_mode_bits & SDRAM_CAS_MASK));
do_ram_command(RAM_COMMAND_MRS, jedec_mode_bits);
}
-/*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
-/* SDRAM CONFIGURATION FUNCTIONS */
-/**********************************************************************************/
-
-//----------------------------------------------------------------------------------
-// Function: configure_dimm_row_boundaries
-// Parameters:
-// dimm_log2_num_bits - log2(number of bits) for each side of the DIMM
-// total_dram_64M_multiple - total DRAM in the system (as a
-// multiple of 64 MB) for DIMMs < dimm_index
-// dimm_index - which DIMM pair is being processed
-// (0..MAX_DIMM_SOCKETS_PER_CHANNEL)
-// Return Value: New multiple of 64 MB total DRAM in the system
-// Description: Configure the E7501's DRAM Row Boundary registers for the memory
-// present in the specified DIMM.
-//
+/*-----------------------------------------------------------------------------
+DIMM-independant configuration functions:
+-----------------------------------------------------------------------------*/
+
+/**
+ * Configure the E7501's DRAM Row Boundary (DRB) registers for the memory
+ * present in the specified DIMM.
+ *
+ * @param dimm_log2_num_bits Specifies log2(number of bits) for each side of
+ * the DIMM.
+ * @param total_dram_64M_multiple Total DRAM in the system (as a multiple of
+ * 64 MB) for DIMMs < dimm_index.
+ * @param dimm_index Which DIMM pair is being processed
+ * (0..MAX_DIMM_SOCKETS_PER_CHANNEL).
+ * @return New multiple of 64 MB total DRAM in the system.
+ */
static uint8_t configure_dimm_row_boundaries(struct dimm_size dimm_log2_num_bits, uint8_t total_dram_64M_multiple, unsigned dimm_index)
{
int i;
ASSERT((dimm_log2_num_bits.side2 == 0)
|| (dimm_log2_num_bits.side2 >= 28));
- // In dual-channel mode, we are called only once for each pair of DIMMs.
+ // In dual-channel mode, we are called only once for each pair of DIMMs.
// Each time we process twice the capacity of a single DIMM.
// Convert single DIMM capacity to paired DIMM capacity
pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_0 + (dimm_index << 1),
total_dram_64M_multiple);
- // If the DIMMs are double-sided, add the capacity of side 2 this DIMM pair
+ // If the DIMMs are double-sided, add the capacity of side 2 this DIMM pair
// (as a multiple of 64 MB) to the total capacity of the system
if (dimm_log2_num_bits.side2 >= 29)
total_dram_64M_multiple +=
return total_dram_64M_multiple;
}
-//----------------------------------------------------------------------------------
-// Function: configure_e7501_ram_addresses
-// Parameters: ctrl - PCI addresses of memory controller functions, and
-// SMBus addresses of DIMM slots on the mainboard
-// dimm_mask - bitmask of populated DIMMs on the board - see
-// spd_get_supported_dimms()
-// Return Value: None
-// Description: Program the E7501's DRAM row boundary addresses and its Top Of
-// Low Memory (TOLM). If necessary, set up a remap window so we
-// don't waste DRAM that ordinarily would lie behind addresses
-// reserved for memory-mapped I/O.
-//
+/**
+ * Set the E7501's DRAM row boundary addresses & its Top Of Low Memory (TOLM).
+ *
+ * If necessary, set up a remap window so we don't waste DRAM that ordinarily
+ * would lie behind addresses reserved for memory-mapped I/O.
+ *
+ * @param ctrl PCI addresses of memory controller functions, and SMBus
+ * addresses of DIMM slots on the mainboard.
+ * @param dimm_mask Bitmask of populated DIMMs, see spd_get_supported_dimms().
+ */
static void configure_e7501_ram_addresses(const struct mem_controller
*ctrl, uint8_t dimm_mask)
{
}
}
-//----------------------------------------------------------------------------------
-// Function: initialize_ecc
-// Parameters: None
-// Return Value: None
-// Description: If we're configured to use ECC, initialize the SDRAM and
-// clear the E7501's ECC error flags.
-//
+/**
+ * If we're configured to use ECC, initialize the SDRAM and clear the E7501's
+ * ECC error flags.
+ */
static void initialize_ecc(void)
{
uint32_t dram_controller_mode;
}
-//----------------------------------------------------------------------------------
-// Function: configure_e7501_dram_timing
-// Parameters: ctrl - PCI addresses of memory controller functions, and
-// SMBus addresses of DIMM slots on the mainboard
-// dimm_mask - bitmask of populated DIMMs on the board - see
-// spd_get_supported_dimms()
-// Return Value: None
-// Description: Program the DRAM Timing register of the E7501 (except for CAS#
-// latency, which is assumed to have been programmed already), based
-// on the parameters of the various installed DIMMs.
-//
+/**
+ * Program the DRAM Timing register (DRT) of the E7501 (except for CAS#
+ * latency, which is assumed to have been programmed already), based on the
+ * parameters of the various installed DIMMs.
+ *
+ * @param ctrl PCI addresses of memory controller functions, and SMBus
+ * addresses of DIMM slots on the mainboard.
+ * @param dimm_mask Bitmask of populated DIMMs, see spd_get_supported_dimms().
+ */
static void configure_e7501_dram_timing(const struct mem_controller *ctrl,
uint8_t dimm_mask)
{
if (slowest_row_precharge > ((22 << 2) | (2 << 0)))
die("unsupported DIMM tRP"); // > 22.5 ns: 4 or more clocks
else if (slowest_row_precharge > (15 << 2))
- dram_timing &= ~(1 << 0); // > 15.0 ns: 3 clocks
+ dram_timing &= ~(1 << 0); // > 15.0 ns: 3 clocks
else
dram_timing |= (1 << 0); // <= 15.0 ns: 2 clocks
if (slowest_ras_cas_delay > ((22 << 2) | (2 << 0)))
die("unsupported DIMM tRCD"); // > 22.5 ns: 4 or more clocks
else if (slowest_ras_cas_delay > (15 << 2))
- dram_timing |= (2 << 1); // > 15.0 ns: 3 clocks
+ dram_timing |= (2 << 1); // > 15.0 ns: 3 clocks
else
dram_timing |= ((1 << 3) | (3 << 1)); // <= 15.0 ns: 2 clocks
if (slowest_active_to_precharge_delay > 52)
die("unsupported DIMM tRAS"); // > 52 ns: 8 or more clocks
else if (slowest_active_to_precharge_delay > 45)
- dram_timing |= (0 << 9); // 46-52 ns: 7 clocks
+ dram_timing |= (0 << 9); // 46-52 ns: 7 clocks
else if (slowest_active_to_precharge_delay > 37)
dram_timing |= (1 << 9); // 38-45 ns: 6 clocks
else
die(SPD_ERROR);
}
-//----------------------------------------------------------------------------------
-// Function: configure_e7501_cas_latency
-// Parameters: ctrl - PCI addresses of memory controller functions, and
-// SMBus addresses of DIMM slots on the mainboard
-// dimm_mask - bitmask of populated DIMMs on the board - see
-// spd_get_supported_dimms()
-// Return Value: None
-// Description: Determine the shortest CAS# latency that the E7501 and all DIMMs
-// have in common, and program the E7501 to use it.
-//
+/**
+ * Determine the shortest CAS# latency that the E7501 and all DIMMs have in
+ * common, and program the E7501 to use it.
+ *
+ * @param ctrl PCI addresses of memory controller functions, and SMBus
+ * addresses of DIMM slots on the mainboard.
+ * @param dimm_mask Bitmask of populated DIMMs, spd_get_supported_dimms().
+ */
static void configure_e7501_cas_latency(const struct mem_controller *ctrl,
uint8_t dimm_mask)
{
die(SPD_ERROR);
}
-//----------------------------------------------------------------------------------
-// Function: configure_e7501_dram_controller_mode
-// Parameters: ctrl - PCI addresses of memory controller functions, and
-// SMBus addresses of DIMM slots on the mainboard
-// dimm_mask - bitmask of populated DIMMs on the board - see
-// spd_get_supported_dimms()
-// Return Value: None
-// Description: Configure the refresh interval so that we refresh no more often
-// than required by the "most needy" DIMM. Also disable ECC if any
-// of the DIMMs don't support it.
-//
+/**
+ * Configure the refresh interval so that we refresh no more often than
+ * required by the "most needy" DIMM. Also disable ECC if any of the DIMMs
+ * don't support it.
+ *
+ * @param ctrl PCI addresses of memory controller functions, and SMBus
+ * addresses of DIMM slots on the mainboard.
+ * @param dimm_mask Bitmask of populated DIMMs, spd_get_supported_dimms().
+ */
static void configure_e7501_dram_controller_mode(const struct
mem_controller *ctrl,
uint8_t dimm_mask)
pci_write_config32(PCI_DEV(0, 0, 0), DRC, controller_mode);
}
-//----------------------------------------------------------------------------------
-// Function: configure_e7501_row_attributes
-// Parameters: ctrl - PCI addresses of memory controller functions, and
-// SMBus addresses of DIMM slots on the mainboard
-// dimm_mask - bitmask of populated DIMMs on the board - see
-// spd_get_supported_dimms()
-// Return Value: None
-// Description: Configure the E7501's DRAM Row Attributes (DRA) registers
-// based on DIMM parameters read via SPD. This tells the controller
-// the width of the SDRAM chips on each DIMM side (x4 or x8) and
-// the page size of each DIMM side (4, 8, 16, or 32 KB).
-//
+/**
+ * Configure the E7501's DRAM Row Attributes (DRA) registers based on DIMM
+ * parameters read via SPD. This tells the controller the width of the SDRAM
+ * chips on each DIMM side (x4 or x8) and the page size of each DIMM side
+ * (4, 8, 16, or 32 KB).
+ *
+ * @param ctrl PCI addresses of memory controller functions, and SMBus
+ * addresses of DIMM slots on the mainboard.
+ * @param dimm_mask Bitmask of populated DIMMs, spd_get_supported_dimms().
+ */
static void configure_e7501_row_attributes(const struct mem_controller
*ctrl, uint8_t dimm_mask)
{
pci_write_config32(PCI_DEV(0, 0, 0), DRA, row_attributes);
}
-//----------------------------------------------------------------------------------
-// Function: enable_e7501_clocks
-// Parameters: dimm_mask - bitmask of populated DIMMs on the board - see
-// spd_get_supported_dimms()
-// Return Value: None
-// Description: Enable clock signals for populated DIMM sockets and disable them
-// for unpopulated sockets (to reduce EMI).
-//
+/*
+ * Enable clock signals for populated DIMM sockets and disable them for
+ * unpopulated sockets (to reduce EMI).
+ *
+ * @param dimm_mask Bitmask of populated DIMMs, see spd_get_supported_dimms().
+ */
static void enable_e7501_clocks(uint8_t dimm_mask)
{
int i;
pci_write_config8(PCI_DEV(0, 0, 0), CKDIS, clock_disable);
}
-/*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
-/* DIMM-DEDEPENDENT CONFIGURATION FUNCTIONS */
-/**********************************************************************************/
-
-//----------------------------------------------------------------------------------
-// Function: RAM_RESET_DDR_PTR
-// Parameters: ctrl - PCI addresses of memory controller functions, and
-// SMBus addresses of DIMM slots on the mainboard
-// Return Value: None
-// Description: DDR Receive FIFO RE-Sync (?)
-//
+/* DIMM-dedependent configuration functions */
+
+/**
+ * DDR Receive FIFO RE-Sync (?)
+ */
static void RAM_RESET_DDR_PTR(void)
{
uint8_t byte;
pci_write_config8(PCI_DEV(0, 0, 0), 0x88, byte);
}
-//----------------------------------------------------------------------------------
-// Function: ram_set_d0f0_regs
-// Parameters: None
-// Return Value: None
-// Description: Set E7501 registers that are either independent of DIMM specifics,
-// or establish default settings that will be overridden when we
-// learn the specifics.
-// This sets PCI configuration registers to known good values based
-// on the table 'constant_register_values', which are a triple of
-// configuration register offset, mask, and bits to set.
-//
+/**
+ * Set E7501 registers that are either independent of DIMM specifics, or
+ * establish default settings that will be overridden when we learn the
+ * specifics.
+ *
+ * This sets PCI configuration registers to known good values based on the
+ * table 'constant_register_values', which are a triple of configuration
+ * register offset, mask, and bits to set.
+ */
static void ram_set_d0f0_regs(void)
{
int i;
}
}
-//----------------------------------------------------------------------------------
-// Function: write_8dwords
-// Parameters: src_addr
-// dst_addr
-// Return Value: None
-// Description: Copy 64 bytes from one location to another.
-//
-static void write_8dwords(const uint32_t * src_addr, uint32_t dst_addr)
+/**
+ * Copy 64 bytes from one location to another.
+ *
+ * @param src_addr TODO
+ * @param dst_addr TODO
+ */
+static void write_8dwords(const uint32_t *src_addr, uint32_t dst_addr)
{
int i;
for (i = 0; i < 8; i++) {
}
}
-//----------------------------------------------------------------------------------
-// Function: ram_set_rcomp_regs
-// Parameters: None
-// Return Value: None
-// Description: Set the E7501's (undocumented) RCOMP registers.
-// Per the 855PM datasheet and IXP2800 HW Initialization Reference
-// Manual, RCOMP registers appear to affect drive strength,
-// pullup/pulldown offset, and slew rate of various signal groups.
-// Comments below are conjecture based on apparent similarity
-// between the E7501 and these two chips.
-//
+/**
+ * Set the E7501's (undocumented) RCOMP registers.
+ *
+ * Per the 855PM datasheet and IXP2800 HW Initialization Reference Manual,
+ * RCOMP registers appear to affect drive strength, pullup/pulldown offset,
+ * and slew rate of various signal groups.
+ *
+ * Comments below are conjecture based on apparent similarity between the
+ * E7501 and these two chips.
+ */
static void ram_set_rcomp_regs(void)
{
uint32_t dword;
}
-/*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
-/* DIMM-INDEPENDENT CONFIGURATION FUNCTIONS */
-/**********************************************************************************/
-
-//----------------------------------------------------------------------------------
-// Function: sdram_enable
-// Parameters: controllers - not used
-// ctrl - PCI addresses of memory controller functions, and
-// SMBus addresses of DIMM slots on the mainboard
-// Return Value: None
-// Description: Go through the JEDEC initialization sequence for all DIMMs,
-// then enable refresh and initialize ECC and memory to zero.
-// Upon exit, SDRAM is up and running.
-//
+/*-----------------------------------------------------------------------------
+Public interface:
+-----------------------------------------------------------------------------*/
+
+/**
+ * Go through the JEDEC initialization sequence for all DIMMs, then enable
+ * refresh and initialize ECC and memory to zero. Upon exit, SDRAM is up
+ * and running.
+ *
+ * @param controllers Not used.
+ * @param ctrl PCI addresses of memory controller functions, and SMBus
+ * addresses of DIMM slots on the mainboard.
+ */
static void sdram_enable(int controllers,
const struct mem_controller *ctrl)
{
DUMPNORTH();
}
-//----------------------------------------------------------------------------------
-// Function: sdram_set_spd_registers
-// Parameters: ctrl - PCI addresses of memory controller functions, and
-// SMBus addresses of DIMM slots on the mainboard
-// Return Value: None
-// Description: Configure SDRAM controller parameters that depend on
-// characteristics of the DIMMs installed in the system. These
-// characteristics are read from the DIMMs via the standard Serial
-// Presence Detect (SPD) interface.
-//
+/**
+ * Configure SDRAM controller parameters that depend on characteristics of the
+ * DIMMs installed in the system. These characteristics are read from the
+ * DIMMs via the standard Serial Presence Detect (SPD) interface.
+ *
+ * @param ctrl PCI addresses of memory controller functions, and SMBus
+ * addresses of DIMM slots on the mainboard.
+ */
static void sdram_set_spd_registers(const struct mem_controller *ctrl)
{
uint8_t dimm_mask;
}
/* NOTE: configure_e7501_ram_addresses() is NOT called here.
- * We want to keep the default 64 MB/row mapping until sdram_enable() is called,
+ * We want to keep the default 64 MB/row mapping until sdram_enable() is called,
* even though the default mapping is almost certainly incorrect.
* The default mapping makes it easy to initialize all of the DIMMs
* even if the total system memory is > 4 GB.
pci_write_config16(PCI_DEV(0, 0, 0), SKPD, dimm_mask);
}
-//----------------------------------------------------------------------------------
-// Function: sdram_set_registers
-// Parameters: ctrl - PCI addresses of memory controller functions, and
-// SMBus addresses of DIMM slots on the mainboard
-// Return Value: None
-// Description: Do basic ram setup that does NOT depend on serial presence detect
-// information (i.e. independent of DIMM specifics).
-//
+/**
+ * Do basic RAM setup that does NOT depend on serial presence detect
+ * information (i.e. independent of DIMM specifics).
+ *
+ * @param ctrl PCI addresses of memory controller functions, and SMBus
+ * addresses of DIMM slots on the mainboard.
+ */
static void sdram_set_registers(const struct mem_controller *ctrl)
{
RAM_DEBUG_MESSAGE("Northbridge prior to SDRAM init:\n");
ram_set_rcomp_regs();
ram_set_d0f0_regs();
}
-
-/*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
-/* PUBLIC INTERFACE */
-/**********************************************************************************/
projects / coreboot.git / blobdiff