-
/* This was originally for the e7500, modified for e7501
- * The primary differences are that 7501 apparently can
+ * The primary differences are that 7501 apparently can
* support single channel RAM (i haven't tested),
* CAS1.5 is no longer supported, The ECC scrubber
* now supports a mode to zero RAM and init ECC in one step
- * and the undocumented registers at 0x80 require new
+ * and the undocumented registers at 0x80 require new
* (undocumented) values determined by guesswork and
* comparison w/ OEM BIOS values.
* Steven James 02/06/2003
/* converted to C 6/2004 yhlu */
-#define DEBUG_RAM_CONFIG 0
-
-#define dumpnorth() dump_pci_device(PCI_DEV(0, 0, 0))
-
-/* DDR DIMM Mode register Definitions */
-
-#define BURST_2 (1<<0)
-#define BURST_4 (2<<0)
-#define BURST_8 (3<<0)
-
-#define BURST_SEQUENTIAL (0<<3)
-#define BURST_INTERLEAVED (1<<3)
-
-#define CAS_2_0 (0x2<<4)
-#define CAS_3_0 (0x3<<4)
-#define CAS_1_5 (0x5<<4)
-#define CAS_2_5 (0x6<<4)
-
-#define MODE_NORM (0 << 7)
-#define MODE_DLL_RESET (2 << 7)
-#define MODE_TEST (1 << 7)
-
-#define BURST_LENGTH BURST_4
-#define BURST_TYPE BURST_INTERLEAVED
-#define CAS_LATENCY CAS_2_0
-//#define CAS_LATENCY CAS_2_5
-//#define CAS_LATENCY CAS_1_5
-
-#define MRS_VALUE (MODE_NORM | CAS_LATENCY | BURST_TYPE | BURST_LENGTH)
-#define EMRS_VALUE 0x000
-
-#define MD_SHIFT 4
-
-#define RAM_COMMAND_NONE 0x0
-#define RAM_COMMAND_NOP 0x1
-#define RAM_COMMAND_PRECHARGE 0x2
-#define RAM_COMMAND_MRS 0x3
-#define RAM_COMMAND_EMRS 0x4
-#define RAM_COMMAND_CBR 0x6
-#define RAM_COMMAND_NORMAL 0x7
-
-
-static inline void do_ram_command (const struct mem_controller *ctrl, uint32_t value) {
- uint32_t dword;
- uint8_t byte;
- int i;
- uint32_t result;
-#if DEBUG_RAM_CONFIG >= 2
- print_debug("P:");
- print_debug_hex8(value);
- print_debug("\r\n");
-#endif
- /* %ecx - initial address to read from */
- /* Compute the offset */
- dword = value >> 16;
- for(i=0;i<8;i++) {
- /* Set the ram command */
- byte = pci_read_config8(ctrl->d0, 0x7c);
- byte &= 0x8f;
- byte |= (uint8_t)(value & 0xff);
- pci_write_config8(ctrl->d0, 0x7c, byte);
-
- /* Assert the command to the memory */
-#if DEBUG_RAM_CONFIG >= 2
- print_debug("R:");
- print_debug_hex32(dword);
- print_debug("\r\n");
+#include <assert.h>
+#include <spd.h>
+#include <sdram_mode.h>
+#include <stdlib.h>
+#include "e7501.h"
+
+// Uncomment this to enable run-time checking of DIMM parameters
+// for dual-channel operation
+// Unfortunately the code seems to chew up several K of space.
+//#define VALIDATE_DIMM_COMPATIBILITY
+
+#if CONFIG_DEBUG_RAM_SETUP
+#define RAM_DEBUG_MESSAGE(x) print_debug(x)
+#define RAM_DEBUG_HEX32(x) print_debug_hex32(x)
+#define RAM_DEBUG_HEX8(x) print_debug_hex8(x)
+#define DUMPNORTH() dump_pci_device(PCI_DEV(0, 0, 0))
+#else
+#define RAM_DEBUG_MESSAGE(x)
+#define RAM_DEBUG_HEX32(x)
+#define RAM_DEBUG_HEX8(x)
+#define DUMPNORTH()
#endif
- result = read32(dword);
-
- /* Go to the next base address */
- dword += 0x04000000;
+#define E7501_SDRAM_MODE (SDRAM_BURST_INTERLEAVED | SDRAM_BURST_4)
+#define SPD_ERROR "Error reading SPD info\n"
- }
+// NOTE: This used to be 0x100000.
+// That doesn't work on systems where A20M# is asserted, because
+// attempts to access 0x1000NN end up accessing 0x0000NN.
+#define RCOMP_MMIO 0x200000
- /* The command has been sent to all dimms so get out */
-}
-
-
-static inline void RAM_CMD(const struct mem_controller *ctrl, uint32_t command, uint32_t offset) {
- uint32_t value = ((offset) << (MD_SHIFT + 16))|((command << 4) & 0x70) ;
- do_ram_command(ctrl, value);
-}
-
-#define RAM_NOP(ctrl) RAM_CMD(ctrl, RAM_COMMAND_NOP, 0)
-#define RAM_PRECHARGE(ctrl) RAM_CMD(ctrl, RAM_COMMAND_PRECHARGE, 0)
-#define RAM_CBR(ctrl) RAM_CMD(ctrl, RAM_COMMAND_CBR, 0)
-#define RAM_EMRS(ctrl) RAM_CMD(ctrl, RAM_COMMAND_EMRS, EMRS_VALUE)
-
-static const uint8_t ram_cas_latency[] = {
- CAS_2_5, CAS_2_0, CAS_1_5, CAS_2_5
- };
-
-static inline void ram_mrs(const struct mem_controller *ctrl, uint32_t value){
- /* Read the cas latency setting */
- uint8_t byte;
- uint32_t dword;
- byte = pci_read_config8(ctrl->d0, 0x78);
- /* Transform it into the form expected by SDRAM */
- dword = ram_cas_latency[(byte>>4) & 3];
-
- value |= (dword<<(16+MD_SHIFT));
-
- value |= (MODE_NORM | BURST_TYPE | BURST_LENGTH) << (16+MD_SHIFT);
-
- do_ram_command(ctrl, value);
-}
-
-#define RAM_MRS(ctrl, dll_reset) ram_mrs( ctrl, (dll_reset << (8+MD_SHIFT+ 16)) | ((RAM_COMMAND_MRS <<4)& 0x70) )
+struct dimm_size {
+ unsigned long side1;
+ unsigned long side2;
+};
-static void RAM_NORMAL(const struct mem_controller *ctrl) {
- uint8_t byte;
- byte = pci_read_config8(ctrl->d0, 0x7c);
- byte &= 0x8f;
- byte |= (RAM_COMMAND_NORMAL << 4);
- pci_write_config8(ctrl->d0, 0x7c, byte);
-}
+/*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
+/* DEFINITIONS */
+/**********************************************************************************/
+
+static const uint32_t refresh_frequency[] = {
+ /* Relative frequency (array value) of each E7501 Refresh Mode Select
+ * (RMS) value (array index)
+ * 0 == least frequent refresh (longest interval between refreshes)
+ * [0] disabled -> 0
+ * [1] 15.6 usec -> 2
+ * [2] 7.8 usec -> 3
+ * [3] 64 usec -> 1
+ * [4] reserved -> 0
+ * [5] reserved -> 0
+ * [6] reserved -> 0
+ * [7] 64 clocks -> 4
+ */
+ 0, 2, 3, 1, 0, 0, 0, 4
+};
-static void RAM_RESET_DDR_PTR(const struct mem_controller *ctrl) {
- uint8_t byte;
- byte = pci_read_config8(ctrl->d0, 0x88);
- byte |= (1 << 4 );
- pci_write_config8(ctrl->d0, 0x88, byte);
- byte = pci_read_config8(ctrl->d0, 0x88);
- byte &= ~(1 << 4);
- pci_write_config8(ctrl->d0, 0x88, byte);
-}
+static const uint32_t refresh_rate_map[] = {
+ /* Map the JEDEC spd refresh rates (array index) to E7501 Refresh Mode
+ * Select values (array value)
+ * These are all the rates defined by JESD21-C Appendix D, Rev. 1.0
+ * The E7501 supports only 15.6 us (1), 7.8 us (2), 64 us (3), and
+ * 64 clock (481 ns) (7) refresh.
+ * [0] == 15.625 us -> 15.6 us
+ * [1] == 3.9 us -> 481 ns
+ * [2] == 7.8 us -> 7.8 us
+ * [3] == 31.3 us -> 15.6 us
+ * [4] == 62.5 us -> 15.6 us
+ * [5] == 125 us -> 64 us
+ */
+ 1, 7, 2, 1, 1, 3
+};
-static void ENABLE_REFRESH(const struct mem_controller *ctrl)
-{
- uint32_t dword;
- dword = pci_read_config32(ctrl->d0, 0x7c);
- dword |= (1 << 29);
- pci_write_config32(ctrl->d0, 0x7c, dword);
-}
+#define MAX_SPD_REFRESH_RATE ((sizeof(refresh_rate_map) / sizeof(uint32_t)) - 1)
+
+// SPD parameters that must match for dual-channel operation
+static const uint8_t dual_channel_parameters[] = {
+ SPD_MEMORY_TYPE,
+ SPD_MODULE_VOLTAGE,
+ SPD_NUM_COLUMNS,
+ SPD_NUM_ROWS,
+ SPD_NUM_DIMM_BANKS,
+ SPD_PRIMARY_SDRAM_WIDTH,
+ SPD_NUM_BANKS_PER_SDRAM
+};
/*
- * Table: constant_register_values
+ * Table: constant_register_values
*/
-static const long register_values[] = {
+static const long constant_register_values[] = {
/* SVID - Subsystem Vendor Identification Register
* 0x2c - 0x2d
* [15:00] Subsytem Vendor ID (Indicates system board vendor)
* 0x2e - 0x2f
* [15:00] Subsystem ID
*/
- 0x2c, 0, (0x15d9 << 0) | (0x3580 << 16),
+ // Not everyone wants to be Super Micro Computer, Inc.
+ // The mainboard should set this if desired.
+ // 0x2c, 0, (0x15d9 << 0) | (0x3580 << 16),
/* Undocumented
- * 0x80 - 0x80
+ * (DRAM Read Timing Control, if similar to 855PM?)
+ * 0x80 - 0x81
* This register has something to do with CAS latencies,
* possibily this is the real chipset control.
* At 0x00 CAS latency 1.5 works.
* CAS 2.0 values taken from Intel BIOS settings, others are a guess
* and may be terribly wrong. Old values preserved as comments until I
* figure this out for sure.
- * e7501 docs claim that CAS1.5 is unsupported, so it may or may not
+ * e7501 docs claim that CAS1.5 is unsupported, so it may or may not
* work at all.
* Steven James 02/06/2003
*/
-#if CAS_LATENCY == CAS_2_5
-// 0x80, 0xfffffe00, 0x06 /* Intel E7500 recommended */
- 0x80, 0xfffff000, 0x0662, /* from Factory Bios */
-#elif CAS_LATENCY == CAS_2_0
-// 0x80, 0xfffffe00, 0x0d /* values for register 0x80 */
- 0x80, 0xfffff000, 0x0bb1, /* values for register 0x80 */
-#endif
-
- /* Enable periodic memory recalibration */
- 0x88, 0xffffff00, 0x80,
+ /* NOTE: values now configured in configure_e7501_cas_latency() based
+ * on SPD info and total number of DIMMs (per Intel)
+ */
/* FDHC - Fixed DRAM Hole Control
* 0x58
* 10 == Write Only (Writes to DRAM, Reads to memory mapped I/O space)
* 11 == Normal (All Access go to DRAM)
*/
+
+ // Map all legacy ranges to DRAM
0x58, 0xcccccf7f, (0x00 << 0) | (0x30 << 8) | (0x33 << 16) | (0x33 << 24),
0x5C, 0xcccccccc, (0x33 << 0) | (0x33 << 8) | (0x33 << 16) | (0x33 << 24),
/* DRB - DRAM Row Boundary Registers
* 0x60 - 0x6F
* An array of 8 byte registers, which hold the ending
- * memory address assigned to each pair of DIMMS, in 64MB
- * granularity.
+ * memory address assigned to each pair of DIMMS, in 64MB
+ * granularity.
*/
- /* Conservatively say each row has 64MB of ram, we will fix this up later */
+ // Conservatively say each row has 64MB of ram, we will fix this up later
+ // NOTE: These defaults allow us to prime all of the DIMMs on the board
+ // without jumping through 36-bit adddressing hoops, even if the
+ // total memory is > 4 GB. Changing these values may break do_ram_command()!
0x60, 0x00000000, (0x01 << 0) | (0x02 << 8) | (0x03 << 16) | (0x04 << 24),
0x64, 0x00000000, (0x05 << 0) | (0x06 << 8) | (0x07 << 16) | (0x08 << 24),
- 0x68, 0xffffffff, 0,
- 0x6C, 0xffffffff, 0,
- /* DRA - DRAM Row Attribute Register
+ /* DRA - DRAM Row Attribute Register
* 0x70 Row 0,1
* 0x71 Row 2,3
- * 0x72 Row 4,5
+ * 0x72 Row 4,5
* 0x73 Row 6,7
* [7:7] Device width for Odd numbered rows
* 0 == 8 bits wide x8
* 1 == 4 bits wide x4
* [6:4] Row Attributes for Odd numbered rows
- * 010 == 8KB
- * 011 == 16KB
- * 100 == 32KB
- * 101 == 64KB
+ * 010 == 8KB (for dual-channel)
+ * 011 == 16KB (for dual-channel)
+ * 100 == 32KB (for dual-channel)
+ * 101 == 64KB (for dual-channel)
* Others == Reserved
* [3:3] Device width for Even numbered rows
* 0 == 8 bits wide x8
* 1 == 4 bits wide x4
* [2:0] Row Attributes for Even numbered rows
- * 010 == 8KB
- * 011 == 16KB
- * 100 == 32KB
+ * 010 == 8KB (for dual-channel)
+ * 011 == 16KB (for dual-channel)
+ * 100 == 32KB (for dual-channel)
* 101 == 64KB (This page size appears broken)
* Others == Reserved
*/
- 0x70, 0x00000000,
- (((0<<3)|(0<<0))<< 0) |
- (((0<<3)|(0<<0))<< 4) |
- (((0<<3)|(0<<0))<< 8) |
- (((0<<3)|(0<<0))<<12) |
- (((0<<3)|(0<<0))<<16) |
- (((0<<3)|(0<<0))<<20) |
- (((0<<3)|(0<<0))<<24) |
- (((0<<3)|(0<<0))<<28),
- 0x74, 0xffffffff, 0,
-
- /* DRT - DRAM Time Register
+ // NOTE: overridden by configure_e7501_row_attributes(), later
+ 0x70, 0x00000000, 0,
+
+ /* DRT - DRAM Timing Register
* 0x78
* [31:30] Reserved
* [29:29] Back to Back Write-Read Turn Around
* Others == Reserved
* [23:19] Reserved
* [18:16] DRAM idle timer
- * 000 == infinite
- * 011 == 16 dram clocks
- * 001 == Datasheet says reserved, but Intel BIOS sets it
+ * 000 == infinite
+ * 011 == 16 dram clocks
+ * 001 == 0 clocks
* [15:11] Reserved
* [10:09] Active to Precharge (tRAS)
* 00 == 7 clocks
* [05:04] Cas Latency (tCL)
* 00 == 2.5 Clocks
* 01 == 2.0 Clocks
- * 10 == 1.5 Clocks
+ * 10 == Reserved (was 1.5 Clocks for E7500)
* 11 == Reserved
* [03:03] Write Ras# to Cas# Delay (tRCD)
* 0 == 3 DRAM Clocks
* 1 == 2 DRAM Clocks
- * [02:01] Read RAS# to CAS# Delay (tRCD)
- * 00 == reserved
- * 01 == reserved
+ * [02:01] Read RAS# to CAS# Delay (tRCD)
+ * 00 == reserved
+ * 01 == reserved
* 10 == 3 DRAM Clocks
* 11 == 2 DRAM Clocks
* [00:00] DRAM RAS# to Precharge (tRP)
* 0 == 3 DRAM Clocks
* 1 == 2 DRAM Clocks
*/
-#define DRT_CAS_2_5 (0<<4)
-#define DRT_CAS_2_0 (1<<4)
-#define DRT_CAS_1_5 (2<<4)
-#define DRT_CAS_MASK (3<<4)
-
-#if CAS_LATENCY == CAS_2_5
-#define DRT_CL DRT_CAS_2_5
-#elif CAS_LATENCY == CAS_2_0
-#define DRT_CL DRT_CAS_2_0
-#elif CAS_LATENCY == CAS_1_5
-#define DRT_CL DRT_CAS_1_5
-#endif
+ // Some earlier settings:
/* Most aggressive settings possible */
-// 0x78, 0xc0fff8c4, (1<<29)|(1<<28)|(1<<27)|(2<<24)|(2<<9)|DRT_CL|(1<<3)|(1<<1)|(1<<0),
-// 0x78, 0xc0f8f8c0, (1<<29)|(1<<28)|(1<<27)|(1<<24)|(1<<16)|(2<<9)|DRT_CL|(1<<3)|(3<<1)|(1<<0),
- 0x78, 0xc0f8f9c0, (1<<29)|(1<<28)|(1<<27)|(1<<24)|(1<<16)|(2<<9)|DRT_CL|(1<<3)|(3<<1)|(1<<0),
+// 0x78, 0xc0fff8c4, (1<<29)|(1<<28)|(1<<27)|(2<<24)|(2<<9)|CAS_LATENCY|(1<<3)|(1<<1)|(1<<0),
+// 0x78, 0xc0f8f8c0, (1<<29)|(1<<28)|(1<<27)|(1<<24)|(1<<16)|(2<<9)|CAS_LATENCY|(1<<3)|(3<<1)|(1<<0),
+// 0x78, 0xc0f8f9c0, (1<<29)|(1<<28)|(1<<27)|(1<<24)|(1<<16)|(2<<9)|CAS_LATENCY|(1<<3)|(3<<1)|(1<<0),
+
+ // The only things we need to set here are DRAM idle timer, Back-to-Back Read Turnaround, and
+ // Back-to-Back Write-Read Turnaround. All others are configured based on SPD.
+ 0x78, 0xD7F8FFFF, (1 << 29) | (1 << 27) | (1 << 16),
/* FIXME why was I attempting to set a reserved bit? */
/* 0x0100040f */
* 0 == Not Complete
* 1 == Complete
* [28:23] Reserved
- * [22:22] Channels
- * 0 == Single channel
- * 1 == Dual Channel
+ * [22:22] Channels
+ * 0 == Single channel
+ * 1 == Dual Channel
* [21:20] DRAM Data Integrity Mode
* 00 == Disabled, no ECC
* 01 == Reserved
* 10 == Error checking, using chip-kill, with correction
* 11 == Reserved
- * [19:18] Reserved
- * Must equal 01
- * [17:17] (Intel Undocumented) should always be set to 1
+ * [19:18] DRB Granularity (Read-Only)
+ * 00 == 32 MB quantities (single channel mode)
+ * 01 == 64 MB quantities (dual-channel mode)
+ * 10 == Reserved
+ * 11 == Reserved
+ * [17:17] (Intel Undocumented) should always be set to 1 (SJM: comment inconsistent with current setting, below)
* [16:16] Command Per Clock - Address/Control Assertion Rule (CPC)
* 0 == 2n Rule
* 1 == 1n rule
* 111 == Refresh every 64 clocks (fast refresh)
* [07:07] Reserved
* [06:04] Mode Select (SMS)
- * 000 == Self Refresh Mode
+ * 000 == Reserved (was Self Refresh Mode in E7500)
* 001 == NOP Command
* 010 == All Banks Precharge
* 011 == Mode Register Set
- * 100 == Extended Mode Register Set
+ * 100 == Extended Mode Register Set
* 101 == Reserved
* 110 == CBR Refresh
* 111 == Normal Operation
* [03:00] Reserved
*/
-// .long 0x7c, 0xffcefcff, (1<<22)|(2 << 20)|(1 << 16)| (0 << 8),
-// .long 0x7c, 0xff8cfcff, (1<<22)|(2 << 20)|(1 << 17)|(1 << 16)| (0 << 8),
-// .long 0x7c, 0xff80fcff, (1<<22)|(2 << 20)|(1 << 18)|(1 << 17)|(1 << 16)| (0 << 8),
- 0x7c, 0xff82fcff, (1<<22)|(2 << 20)|(1 << 18)|(1 << 16)| (0 << 8),
-
-
- /* Another Intel undocumented register */
- 0x88, 0x080007ff, (1<<31)|(1 << 30)|(1<<28)|(0 << 26)|(0x10 << 21)|(10 << 16)|(0x13 << 11),
+// .long 0x7c, 0xffcefcff, (1<<22)|(2 << 20)|(1 << 16)| (0 << 8),
+// .long 0x7c, 0xff8cfcff, (1<<22)|(2 << 20)|(1 << 17)|(1 << 16)| (0 << 8),
+// .long 0x7c, 0xff80fcff, (1<<22)|(2 << 20)|(1 << 18)|(1 << 17)|(1 << 16)| (0 << 8),
+
+ // Default to dual-channel mode, ECC, 1-clock address/cmd hold
+ // NOTE: configure_e7501_dram_controller_mode() configures further
+ 0x7c, 0xff8ef8ff, (1 << 22) | (2 << 20) | (1 << 16) | (0 << 8),
+
+ /* Another Intel undocumented register
+ * 0x88 - 0x8B
+ * [31:31] Purpose unknown
+ * [26:26] Master DLL Reset?
+ * 0 == Normal operation?
+ * 1 == Reset?
+ * [07:07] Periodic memory recalibration?
+ * 0 == Disabled?
+ * 1 == Enabled?
+ * [04:04] Receive FIFO RE-Sync?
+ * 0 == Normal operation?
+ * 1 == Reset?
+ */
+ // NOTE: Some factory BIOSs don't do this.
+ // Doesn't seem to matter either way.
+ 0x88, 0xffffff00, 0x80,
/* CLOCK_DIS - CK/CK# Disable Register
* 0x8C
- * [7:4] Reserved
+ * [7:7] DDR Frequency
+ * 0 == 100 MHz (200 MHz data rate)
+ * 1 == 133 MHz (266 MHz data rate)
+ * [6:4] Reserved
* [3:3] CK3
* 0 == Enable
* 1 == Disable
* 0 == Enable
* 1 == Disable
*/
+ // NOTE: Disable all clocks initially; turn ones we need back on
+ // in enable_e7501_clocks()
0x8C, 0xfffffff0, 0xf,
/* TOLM - Top of Low Memory Register
* [09:00] Remap Base Address [35:26] 64M aligned
* Bits [25:0] are assumed to be 0.
*/
+
+ // NOTE: TOLM overridden by configure_e7501_ram_addresses()
0xc4, 0xfc0007ff, (0x2000 << 0) | (0x3ff << 16),
+
/* REMAPLIMIT - Remap Limit Address Register
* 0xC8 - 0xC9
* [15:10] Reserved
* [09:00] Remap Limit Address [35:26] 64M aligned
- * When remaplimit < remapbase this register is disabled.
+ * When remaplimit < remapbase the remap window is disabled.
*/
0xc8, 0xfffffc00, 0,
/* DVNP - Device Not Present Register
* 0xE0 - 0xE1
* [15:05] Reserved
- * [04:04] Device 4 Function 1 Present
+ * [04:04] Device 4 Function 1 Present
* 0 == Present
* 1 == Absent
- * [03:03] Device 3 Function 1 Present
+ * [03:03] Device 3 Function 1 Present
* 0 == Present
* 1 == Absent
- * [02:02] Device 2 Function 1 Present
+ * [02:02] Device 2 Function 1 Present
* 0 == Present
* 1 == Absent
- * [01:01] Reserved
- * [00:00] Device 0 Function 1 Present
+ * [01:01] Reserved
+ * [00:00] Device 0 Function 1 Present
* 0 == Present
* 1 == Absent
*/
- 0xe0, 0xffffffe2, (1<<4)|(1<<3)|(1<<2)|(0<<0),
+
+ // Enable D0:D1, disable D2:F1, D3:F1, D4:F1
+ 0xe0, 0xffffffe2, (1 << 4) | (1 << 3) | (1 << 2) | (0 << 0),
+
+ // Undocumented
0xd8, 0xffff9fff, 0x00000000,
+
+ // Undocumented - this is pure conjecture based on similarity to 855PM
+ /* MCHTST - MCH Test Register
+ * 0xF4 - 0xF7
+ * [31:31] Purpose unknown
+ * [30:30] Purpose unknown
+ * [29:23] Unknown - not used?
+ * [22:22] System Memory MMR Enable
+ * 0 == Disable: mem space and BAR at 0x14 are not accessible
+ * 1 == Enable: mem space and BAR at 0x14 are accessible
+ * [21:20] Purpose unknown
+ * [19:02] Unknown - not used?
+ * [01:01] D6EN (Device #6 enable)
+ * 0 == Disable
+ * 1 == Enable
+ * [00:00] Unknown - not used?
+ */
+
0xf4, 0x3f8ffffd, 0x40300002,
+
+#ifdef SUSPICIOUS_LOOKING_CODE
+ // SJM: Undocumented.
+ // This will access D2:F0:0x50, is this correct??
0x1050, 0xffffffcf, 0x00000030,
+#endif
};
+ /* DDR RECOMP tables */
- /*
- * Routine: ram_set_registers
- * Arguments: none
- * Results: none
- * Trashed: %eax, %ebx, %ecx, %edx, %esi, %eflags
- * Effects: Do basic ram setup that does not depend on serial
- * presence detect information.
- * This sets PCI configuration registers to known good
- * values based on the table:
- * constant_register_values
- * Which are a triple of configuration regiser, mask, and value.
- *
- */
-/* from 1M or 512K */
-#define RCOMP_MMIO 0x100000
-
- /* DDR RECOMP table */
-
-static const long ddr_rcomp_1[] = {
+// Slew table for 1x drive?
+static const uint32_t maybe_1x_slew_table[] = {
0x44332211, 0xc9776655, 0xffffffff, 0xffffffff,
0x22111111, 0x55444332, 0xfffca876, 0xffffffff,
};
-static const long ddr_rcomp_2[] = {
+
+// Slew table for 2x drive?
+static const uint32_t maybe_2x_slew_table[] = {
0x00000000, 0x76543210, 0xffffeca8, 0xffffffff,
0x21000000, 0xa8765432, 0xffffffec, 0xffffffff,
};
-static const long ddr_rcomp_3[] = {
+
+// Pull Up / Pull Down offset table, if analogous to IXP2800?
+static const uint32_t maybe_pull_updown_offset_table[] = {
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
0x88888888, 0x88888888, 0x88888888, 0x88888888,
};
-#define rcomp_init_str "Setting RCOMP registers.\r\n"
+/*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
+/* TABLES */
+/**********************************************************************************/
+#define SLOW_DOWN_IO inb(0x80)
+//#define SLOW_DOWN_IO udelay(40);
+
+ /* Estimate that SLOW_DOWN_IO takes about 50&76us */
+ /* delay for 200us */
-static void write_8dwords(uint32_t src_addr, uint32_t dst_addr) {
+#if 1
+static void do_delay(void)
+{
int i;
- uint32_t dword;
- for(i=0;i<8;i++) {
- dword = read32(src_addr);
- write32(dst_addr, dword);
- src_addr+=4;
- dst_addr+=4;
-
+ for (i = 0; i < 16; i++) {
+ SLOW_DOWN_IO;
}
}
-#if 1
-#define SLOW_DOWN_IO inb(0x80);
+#define DO_DELAY do_delay()
#else
-#define SLOW_DOWN_IO udelay(40);
+#define DO_DELAY \
+ udelay(200)
#endif
-static void ram_set_rcomp_regs(const struct mem_controller *ctrl) {
- uint32_t dword;
-#if DEBUG_RAM_CONFIG
- print_debug(rcomp_init_str);
-#endif
+#define EXTRA_DELAY DO_DELAY
- /*enable access to the rcomp bar */
- dword = pci_read_config32(ctrl->d0, 0x0f4);
- dword &= ~(1<<31);
- dword |=((1<<30)|1<<22);
- pci_write_config32(ctrl->d0, 0x0f4, dword);
-
+/*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
+/* DELAY FUNCTIONS */
+/**********************************************************************************/
- /* Set the MMIO address to 512K */
- pci_write_config32(ctrl->d0, 0x14, RCOMP_MMIO);
+static void die_on_spd_error(int spd_return_value)
+{
+ if (spd_return_value < 0)
+ die("Error reading SPD info\n");
+}
- dword = read32(RCOMP_MMIO + 0x20);
- dword |= (1<<9);
- write32(RCOMP_MMIO + 0x20, dword);
-
+//----------------------------------------------------------------------------------
+// Function: sdram_spd_get_page_size
+// Parameters: dimm_socket_address - SMBus address of DIMM socket to interrogate
+// Return Value: struct dimm_size - log2(page size) for each side of the DIMM.
+// Description: Calculate the page size for each physical bank of the DIMM:
+// log2(page size) = (# columns) + log2(data width)
+//
+// NOTE: page size is the total number of data bits in a row.
+//
+static struct dimm_size sdram_spd_get_page_size(uint16_t
+ dimm_socket_address)
+{
+ uint16_t module_data_width;
+ int value;
+ struct dimm_size pgsz;
- /* Begin to write the RCOMP registers */
-
- write8(RCOMP_MMIO + 0x2c, 0xff);
- write32(RCOMP_MMIO + 0x30, 0x01040444);
- write8(RCOMP_MMIO + 0x34, 0x04);
- write32(RCOMP_MMIO + 0x40, 0);
- write16(RCOMP_MMIO + 0x44, 0);
- write16(RCOMP_MMIO + 0x48, 0);
- write16(RCOMP_MMIO + 0x50, 0);
- write_8dwords((uint32_t)ddr_rcomp_1, RCOMP_MMIO + 0x60);
- write_8dwords((uint32_t)ddr_rcomp_2, RCOMP_MMIO + 0x80);
- write_8dwords((uint32_t)ddr_rcomp_2, RCOMP_MMIO + 0xa0);
- write_8dwords((uint32_t)ddr_rcomp_2, RCOMP_MMIO + 0x140);
- write_8dwords((uint32_t)ddr_rcomp_2, RCOMP_MMIO + 0x1c0);
- write_8dwords((uint32_t)ddr_rcomp_3, RCOMP_MMIO + 0x180);
-
-#if 0 /* Print the RCOMP registers */
- movl $RCOMP_MMIO, %ecx
-1: movl %ecx, %eax
- andb $0x0f, %al
- jnz 2f
- CONSOLE_INFO_TX_CHAR($'\r')
- CONSOLE_INFO_TX_CHAR($'\n')
- CONSOLE_INFO_TX_HEX32(%ecx)
- CONSOLE_INFO_TX_CHAR($' ')
- CONSOLE_INFO_TX_CHAR($'-')
- CONSOLE_INFO_TX_CHAR($' ')
-2: movl (%ecx), %eax
- CONSOLE_INFO_TX_HEX32(%eax)
- CONSOLE_INFO_TX_CHAR($' ')
- addl $4, %ecx
- cmpl $(RCOMP_MMIO + 0x1e0), %ecx
- jnz 1b
- CONSOLE_INFO_TX_CHAR($'\r')
- CONSOLE_INFO_TX_CHAR($'\n')
-#endif
+ pgsz.side1 = 0;
+ pgsz.side2 = 0;
- dword = read32(RCOMP_MMIO + 0x20);
- dword &= ~(3);
- dword |= 1;
- write32(RCOMP_MMIO + 0x20, dword);
+ // Side 1
+ value = spd_read_byte(dimm_socket_address, SPD_NUM_COLUMNS);
+ if (value < 0)
+ goto hw_err;
+ pgsz.side1 = value & 0xf; // # columns in bank 1
- /* Wait 40 usec */
- SLOW_DOWN_IO;
-
- /* unblock updates */
- dword = read32(RCOMP_MMIO + 0x20);
- dword &= ~(1<<9);
- write32(RCOMP_MMIO+0x20, dword);
- dword |= (1<<8);
- write32(RCOMP_MMIO+0x20, dword);
- dword &= ~(1<<8);
- write32(RCOMP_MMIO+0x20, dword);
-
- /* Wait 40 usec */
- SLOW_DOWN_IO;
+ /* Get the module data width and convert it to a power of two */
+ value =
+ spd_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_MSB);
+ if (value < 0)
+ goto hw_err;
+ module_data_width = (value & 0xff) << 8;
- /*disable access to the rcomp bar */
- dword = pci_read_config32(ctrl->d0, 0x0f4);
- dword &= ~(1<<22);
- pci_write_config32(ctrl->d0, 0x0f4, dword);
+ value =
+ spd_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_LSB);
+ if (value < 0)
+ goto hw_err;
+ module_data_width |= (value & 0xff);
+
+ pgsz.side1 += log2(module_data_width);
+ /* side two */
+ value = spd_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS);
+ if (value < 0)
+ goto hw_err;
+ if (value > 2)
+ die("Bad SPD value\n");
+ if (value == 2) {
+
+ pgsz.side2 = pgsz.side1; // Assume symmetric banks until we know differently
+ value =
+ spd_read_byte(dimm_socket_address, SPD_NUM_COLUMNS);
+ if (value < 0)
+ goto hw_err;
+ if ((value & 0xf0) != 0) {
+ // Asymmetric banks
+ pgsz.side2 -= value & 0xf; /* Subtract out columns on side 1 */
+ pgsz.side2 += (value >> 4) & 0xf; /* Add in columns on side 2 */
+ }
+ }
+
+ return pgsz;
+
+ hw_err:
+ die(SPD_ERROR);
+ return pgsz; // Never reached
}
-static void ram_set_d0f0_regs(const struct mem_controller *ctrl) {
-#if DEBUG_RAM_CONFIG
- dumpnorth();
-#endif
- int i;
- int max;
- max = sizeof(register_values)/sizeof(register_values[0]);
- for(i = 0; i < max; i += 3) {
- uint32_t reg;
-#if DEBUG_RAM_CONFIG
- print_debug_hex32(register_values[i]);
- print_debug(" <-");
- print_debug_hex32(register_values[i+2]);
- print_debug("\r\n");
-#endif
- reg = pci_read_config32(ctrl->d0,register_values[i]);
- reg &= register_values[i+1];
- reg |= register_values[i+2] & ~(register_values[i+1]);
- pci_write_config32(ctrl->d0,register_values[i], reg);
+//----------------------------------------------------------------------------------
+// Function: sdram_spd_get_width
+// Parameters: dimm_socket_address - SMBus address of DIMM socket to interrogate
+// Return Value: dimm_size - width in bits of each DIMM side's DRAMs.
+// Description: Read the width in bits of each DIMM side's DRAMs via SPD.
+// (i.e. 4, 8, 16)
+//
+static struct dimm_size sdram_spd_get_width(uint16_t dimm_socket_address)
+{
+ int value;
+ struct dimm_size width;
+
+ width.side1 = 0;
+ width.side2 = 0;
+
+ value =
+ spd_read_byte(dimm_socket_address, SPD_PRIMARY_SDRAM_WIDTH);
+ die_on_spd_error(value);
+ width.side1 = value & 0x7f; // Mask off bank 2 flag
- }
-#if DEBUG_RAM_CONFIG
- dumpnorth();
+ if (value & 0x80) {
+ width.side2 = width.side1 << 1; // Bank 2 exists and is double-width
+ } else {
+ // If bank 2 exists, it's the same width as bank 1
+ value =
+ spd_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS);
+ die_on_spd_error(value);
+
+#ifdef ROMCC_IF_BUG_FIXED
+ if (value == 2)
+ width.side2 = width.side1;
+#else
+ switch (value) {
+ case 2:
+ width.side2 = width.side1;
+ break;
+
+ default:
+ break;
+ }
#endif
-}
-static void sdram_set_registers(const struct mem_controller *ctrl){
- ram_set_rcomp_regs(ctrl);
- ram_set_d0f0_regs(ctrl);
-}
+ }
+ return width;
+}
- /*
- * Routine: sdram_spd_get_page_size
- * Arguments: %bl SMBUS_MEM_DEVICE
- * Results:
- * %edi log base 2 page size of DIMM side 1 in bits
- * %esi log base 2 page size of DIMM side 2 in bits
- *
- * Preserved: %ebx (except %bh), %ebp
- *
- * Trashed: %eax, %bh, %ecx, %edx, %esp, %eflags
- * Used: %eax, %ebx, %ecx, %edx, %esi, %edi, %esp, %eflags
- *
- * Effects: Uses serial presence detect to set %edi & %esi
- * to the page size of a dimm.
- * Notes:
- * %bl SMBUS_MEM_DEVICE
- * %edi holds the page size for the first side of the DIMM.
- * %esi holds the page size for the second side of the DIMM.
- * memory size is represent as a power of 2.
- *
- * This routine may be worth moving into generic code somewhere.
- */
-struct dimm_page_size {
- unsigned long side1;
- unsigned long side2;
-};
-
-static struct dimm_page_size sdram_spd_get_page_size(unsigned device) {
-
- uint32_t ecx;
+//----------------------------------------------------------------------------------
+// Function: spd_get_dimm_size
+// Parameters: dimm_socket_address - SMBus address of DIMM socket to interrogate
+// Return Value: dimm_size - log2(number of bits) for each side of the DIMM
+// Description: Calculate the log base 2 size in bits of both DIMM sides.
+// log2(# bits) = (# columns) + log2(data width) +
+// (# rows) + log2(banks per SDRAM)
+//
+// Note that it might be easier to use SPD byte 31 here, it has the
+// DIMM size as a multiple of 4MB. The way we do it now we can size
+// both sides of an asymmetric dimm.
+//
+static struct dimm_size spd_get_dimm_size(unsigned dimm_socket_address)
+{
int value;
- struct dimm_page_size pgsz;
- pgsz.side1 = 0;
- pgsz.side2 = 0;
-
- value = spd_read_byte(device, 4); /* columns */
- if(value < 0) goto hw_err;
- pgsz.side1 = value & 0xf;
-
- /* Get the module data width and convert it to a power of two */
- value = spd_read_byte(device,7); /* (high byte) */
- if(value < 0) goto hw_err;
- ecx = value & 0xff;
- ecx <<= 8;
+ // Start with log2(page size)
+ struct dimm_size sz = sdram_spd_get_page_size(dimm_socket_address);
- value = spd_read_byte(device, 6); /* (low byte) */
- if(value < 0) goto hw_err;
- ecx |= (value & 0xff);
+ if (sz.side1 > 0) {
- pgsz.side1 += log2(ecx); /* compute cheap log base 2 */
+ value = spd_read_byte(dimm_socket_address, SPD_NUM_ROWS);
+ die_on_spd_error(value);
- /* side two */
- value = spd_read_byte(device, 5); /* number of physical banks */
- if(value < 0) goto hw_err;
- if(value==1) goto out;
- if(value!=2) goto val_err;
-
- /* Start with the symmetrical case */
- pgsz.side2 = pgsz.side1;
- value = spd_read_byte(device,4); /* columns */
- if(value < 0) goto hw_err;
- if((value & 0xf0)==0 ) goto out;
- pgsz.side2 -=value & 0xf; /* Subtract out columns on side 1 */
- pgsz.side2 +=(value>>4)& 0xf; /* Add in columns on side 2 */
- goto out;
-
- val_err:
- die("Bad SPD value\r\n");
- /* If an hw_error occurs report that I have no memory */
-hw_err:
- pgsz.side1 = 0;
- pgsz.side2 = 0;
-out:
- return pgsz;
-}
+ sz.side1 += value & 0xf;
+ if (sz.side2 > 0) {
- /*
- * Routine: sdram_spd_get_width
- * Arguments: %bl SMBUS_MEM_DEVICE
- * Results:
- * %edi width of SDRAM chips on DIMM side 1 in bits
- * %esi width of SDRAM chips on DIMM side 2 in bits
- *
- * Preserved: %ebx (except %bh), %ebp
- *
- * Trashed: %eax, %bh, %ecx, %edx, %esp, %eflags
- * Used: %eax, %ebx, %ecx, %edx, %esi, %edi, %esp, %eflags
- *
- * Effects: Uses serial presence detect to set %edi & %esi
- * to the width of a dimm.
- * Notes:
- * %bl SMBUS_MEM_DEVICE
- * %edi holds the width for the first side of the DIMM.
- * %esi holds the width for the second side of the DIMM.
- * memory size is represent as a power of 2.
- *
- * This routine may be worth moving into generic code somewhere.
- */
-struct dimm_width {
- unsigned side1;
- unsigned side2;
-};
-
-static struct dimm_width sdram_spd_get_width(unsigned device) {
- int value;
- struct dimm_width wd;
- uint32_t ecx;
-
- wd.side1 = 0;
- wd.side2 = 0;
-
- value = spd_read_byte(device, 13); /* sdram width */
- if(value < 0 ) goto hw_err;
- ecx = value;
-
- wd.side1 = value & 0x7f;
-
- /* side two */
- value = spd_read_byte(device, 5); /* number of physical banks */
- if(value < 0 ) goto hw_err;
- if(value <=1 ) goto out;
-
- /* Start with the symmetrical case */
- wd.side2 = wd.side1;
-
- if((ecx & 0x80)==0) goto out;
-
- wd.side2 <<=1;
-hw_err:
- wd.side1 = 0;
- wd.side2 = 0;
-
- out:
- return wd;
-}
-
- /*
- * Routine: sdram_spd_get_dimm_size
- * Arguments: %bl SMBUS_MEM_DEVICE
- * Results:
- * %edi log base 2 size of DIMM side 1 in bits
- * %esi log base 2 size of DIMM side 2 in bits
- *
- * Preserved: %ebx (except %bh), %ebp
- *
- * Trashed: %eax, %bh, %ecx, %edx, %esp, %eflags
- * Used: %eax, %ebx, %ecx, %edx, %esi, %edi, %esp, %eflags
- *
- * Effects: Uses serial presence detect to set %edi & %esi
- * the size of a dimm.
- * Notes:
- * %bl SMBUS_MEM_DEVICE
- * %edi holds the memory size for the first side of the DIMM.
- * %esi holds the memory size for the second side of the DIMM.
- * memory size is represent as a power of 2.
- *
- * This routine may be worth moving into generic code somewhere.
- */
+ // Double-sided DIMM
+ if (value & 0xF0)
+ sz.side2 += value >> 4; // Asymmetric
+ else
+ sz.side2 += value; // Symmetric
+ }
-struct dimm_size {
- unsigned long side1;
- unsigned long side2;
-};
+ value =
+ spd_read_byte(dimm_socket_address,
+ SPD_NUM_BANKS_PER_SDRAM);
+ die_on_spd_error(value);
+
+ value = log2(value);
+ sz.side1 += value;
+ if (sz.side2 > 0)
+ sz.side2 += value;
+ }
+
+ return sz;
+}
-static struct dimm_size spd_get_dimm_size(unsigned device)
+#ifdef VALIDATE_DIMM_COMPATIBILITY
+//----------------------------------------------------------------------------------
+// Function: are_spd_values_equal
+// Parameters: spd_byte_number -
+// dimmN_address - SMBus addresses of DIMM sockets to interrogate
+// Return Value: 1 if both DIMM sockets report the same value for the specified
+// SPD parameter; 0 if the values differed or an error occurred.
+// Description: Determine whether two DIMMs have the same value for a SPD parameter.
+//
+static uint8_t are_spd_values_equal(uint8_t spd_byte_number,
+ uint16_t dimm0_address,
+ uint16_t dimm1_address)
{
- /* Calculate the log base 2 size of a DIMM in bits */
- struct dimm_size sz;
- int value, low;
- sz.side1 = 0;
- sz.side2 = 0;
-
- /* Note it might be easier to use byte 31 here, it has the DIMM size as
- * a multiple of 4MB. The way we do it now we can size both
- * sides of an assymetric dimm.
- */
- value = spd_read_byte(device, 3); /* rows */
- if (value < 0) goto hw_err;
-// if ((value & 0xf) == 0) goto val_err;
- sz.side1 += value & 0xf;
-
- value = spd_read_byte(device, 4); /* columns */
- if (value < 0) goto hw_err;
-// if ((value & 0xf) == 0) goto val_err;
- sz.side1 += value & 0xf;
-
- value = spd_read_byte(device, 17); /* banks */
- if (value < 0) goto hw_err;
-// if ((value & 0xff) == 0) goto val_err;
- value &=0xff;
- sz.side1 += log2(value);
-
- /* Get the module data width and convert it to a power of two */
- value = spd_read_byte(device, 7); /* (high byte) */
- if (value < 0) goto hw_err;
- value &= 0xff;
- value <<= 8;
-
- low = spd_read_byte(device, 6); /* (low byte) */
- if (low < 0) goto hw_err;
- value |= (low & 0xff);
-// if ((value != 72) && (value != 64)) goto val_err;
- sz.side1 += log2(value);
-
- /* side 2 */
- value = spd_read_byte(device, 5); /* number of physical banks */
- if (value < 0) goto hw_err;
- if (value == 1) goto out;
-// if (value != 2) goto val_err;
-
- /* Start with the symmetrical case */
- sz.side2 = sz.side1;
-
- value = spd_read_byte(device, 3); /* rows */
- if (value < 0) goto hw_err;
- if ((value & 0xf0) == 0) goto out; /* If symmetrical we are done */
- sz.side2 -= (value & 0x0f); /* Subtract out rows on side 1 */
- sz.side2 += ((value >> 4) & 0x0f); /* Add in rows on side 2 */
-
- value = spd_read_byte(device, 4); /* columns */
- if (value < 0) goto hw_err;
-// if ((value & 0xff) == 0) goto val_err;
- sz.side2 -= (value & 0x0f); /* Subtract out columns on side 1 */
- sz.side2 += ((value >> 4) & 0x0f); /* Add in columsn on side 2 */
- goto out;
-
- val_err:
- die("Bad SPD value\r\n");
- /* If an hw_error occurs report that I have no memory */
-hw_err:
- sz.side1 = 0;
- sz.side2 = 0;
- out:
- return sz;
+ uint8_t bEqual = 0;
+
+ int dimm0_value = spd_read_byte(dimm0_address, spd_byte_number);
+ int dimm1_value = spd_read_byte(dimm1_address, spd_byte_number);
+
+ if ((dimm0_value >= 0) && (dimm1_value >= 0)
+ && (dimm0_value == dimm1_value))
+ bEqual = 1;
+
+ return bEqual;
}
+#endif
+//----------------------------------------------------------------------------------
+// Function: spd_get_supported_dimms
+// Parameters: ctrl - PCI addresses of memory controller functions, and
+// SMBus addresses of DIMM slots on the mainboard
+// Return Value: uint8_t - a bitmask indicating which of the possible sockets
+// for each channel was found to contain a compatible DIMM.
+// Bit 0 corresponds to the closest socket for channel 0,
+// Bit 1 to the next socket for channel 0,
+// ...
+// Bit MAX_DIMM_SOCKETS_PER_CHANNEL-1 to the last socket for channel 0,
+// Bit MAX_DIMM_SOCKETS_PER_CHANNEL is the closest socket for channel 1,
+// ...
+// Bit 2*MAX_DIMM_SOCKETS_PER_CHANNEL-1 is the last socket for channel 1
+// Description: Scan for compatible DIMMs.
+// The code in this module only supports dual-channel operation,
+// so we test that compatible DIMMs are paired.
+//
+static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl)
+{
+ int i;
+ uint8_t dimm_mask = 0;
+ // Have to increase size of dimm_mask if this assertion is violated
+ ASSERT(MAX_DIMM_SOCKETS_PER_CHANNEL <= 4);
- /*
- * This is a place holder fill this out
- * Routine: spd_set_row_attributes
- * Arguments: %bl SMBUS_MEM_DEVICE
- * Results:
- * %edi log base 2 size of DIMM side 1 in bits
- * %esi log base 2 size of DIMM side 2 in bits
- *
- * Preserved: %ebx (except %bh), %ebp
- *
- * Trashed: %eax, %bh, %ecx, %edx, %esp, %eflags
- * Used: %eax, %ebx, %ecx, %edx, %esi, %edi, %esp, %eflags
- *
- * Effects: Uses serial presence detect to set %edi & %esi
- * the size of a dimm.
- * Notes:
- * %bl SMBUS_MEM_DEVICE
- * %edi holds the memory size for the first side of the DIMM.
- * %esi holds the memory size for the second side of the DIMM.
- * memory size is represent as a power of 2.
- *
- * This routine may be worth moving into generic code somewhere.
- */
-static long spd_set_row_attributes(const struct mem_controller *ctrl, long dimm_mask) {
- int i;
- uint32_t dword=0;
- int value;
-
-
- /* Walk through all dimms and find the interesection of the support
- * for ecc sdram and refresh rates
- */
-
-
- for(i = 0; i < DIMM_SOCKETS; i++) {
- if (!(dimm_mask & (1 << i))) {
- continue;
- }
- /* Test to see if I have ecc sdram */
- struct dimm_page_size sz;
- sz = sdram_spd_get_page_size(ctrl->channel0[i]); /* SDRAM type */
-#if DEBUG_RAM_CONFIG
- print_debug("page size =");
- print_debug_hex32(sz.side1);
- print_debug(" ");
- print_debug_hex32(sz.side2);
- print_debug("\r\n");
+ // Find DIMMs we can support on channel 0.
+ // Then see if the corresponding channel 1 DIMM has the same parameters,
+ // since we only support dual-channel.
+
+ for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
+
+ uint16_t channel0_dimm = ctrl->channel0[i];
+ uint16_t channel1_dimm = ctrl->channel1[i];
+ uint8_t bDualChannel = 1;
+#ifdef VALIDATE_DIMM_COMPATIBILITY
+ struct dimm_size page_size;
+ struct dimm_size sdram_width;
#endif
-
- /* Test to see if the dimm is present */
- if( sz.side1 !=0) {
+ int spd_value;
+
+ if (channel0_dimm == 0)
+ continue; // No such socket on this mainboard
+
+ if (spd_read_byte(channel0_dimm, SPD_MEMORY_TYPE) !=
+ SPD_MEMORY_TYPE_SDRAM_DDR)
+ continue;
+
+#ifdef VALIDATE_DIMM_COMPATIBILITY
+ if (spd_read_byte(channel0_dimm, SPD_MODULE_VOLTAGE) !=
+ SPD_VOLTAGE_SSTL2)
+ continue; // Unsupported voltage
+
+ // E7501 does not support unregistered DIMMs
+ spd_value =
+ spd_read_byte(channel0_dimm, SPD_MODULE_ATTRIBUTES);
+ if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0))
+ continue;
+
+ // Must support burst = 4 for dual-channel operation on E7501
+ // NOTE: for single-channel, burst = 8 is required
+ spd_value =
+ spd_read_byte(channel0_dimm,
+ SPD_SUPPORTED_BURST_LENGTHS);
+ if (!(spd_value & SPD_BURST_LENGTH_4) || (spd_value < 0))
+ continue;
+
+ page_size = sdram_spd_get_page_size(channel0_dimm);
+ sdram_width = sdram_spd_get_width(channel0_dimm);
+
+ // Validate DIMM page size
+ // The E7501 only supports page sizes of 4, 8, 16, or 32 KB per channel
+ // NOTE: 4 KB = 32 Kb = 2^15
+ // 32 KB = 262 Kb = 2^18
+
+ if ((page_size.side1 < 15) || (page_size.side1 > 18))
+ continue;
+
+ // If DIMM is double-sided, verify side2 page size
+ if (page_size.side2 != 0) {
+ if ((page_size.side2 < 15)
+ || (page_size.side2 > 18))
+ continue;
+ }
+ // Validate SDRAM width
+ // The E7501 only supports x4 and x8 devices
+
+ if ((sdram_width.side1 != 4) && (sdram_width.side1 != 8))
+ continue;
+
+ // If DIMM is double-sided, verify side2 width
+ if (sdram_width.side2 != 0) {
+ if ((sdram_width.side2 != 4)
+ && (sdram_width.side2 != 8))
+ continue;
+ }
+#endif
+ // Channel 0 DIMM looks compatible.
+ // Now see if it is paired with the proper DIMM on channel 1.
+
+ ASSERT(channel1_dimm != 0); // No such socket on this mainboard??
- /* Test for a valid dimm width */
- if((sz.side1 <15) || (sz.side1>18) ) {
- print_err("unsupported page size\r\n");
+ // NOTE: unpopulated DIMMs cause read to fail
+ spd_value =
+ spd_read_byte(channel1_dimm, SPD_MODULE_ATTRIBUTES);
+ if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0)) {
+
+ print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n");
+ continue;
+ }
+#ifdef VALIDATE_DIMM_COMPATIBILITY
+ spd_value =
+ spd_read_byte(channel1_dimm,
+ SPD_SUPPORTED_BURST_LENGTHS);
+ if (!(spd_value & SPD_BURST_LENGTH_4) || (spd_value < 0))
+ continue;
+
+ int j;
+ for (j = 0; j < sizeof(dual_channel_parameters); ++j) {
+ if (!are_spd_values_equal
+ (dual_channel_parameters[j], channel0_dimm,
+ channel1_dimm)) {
+
+ bDualChannel = 0;
+ break;
}
+ }
+#endif
+
+ // Code around ROMCC bug in optimization of "if" statements
+#ifdef ROMCC_IF_BUG_FIXED
+ if (bDualChannel) {
+ // Made it through all the checks, this DIMM pair is usable
+ dimm_mask |= ((1 << i) | (1 << (MAX_DIMM_SOCKETS_PER_CHANNEL + i)));
+ } else
+ print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n");
+#else
+ switch (bDualChannel) {
+ case 0:
+ print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n");
+ break;
+
+ default:
+ // Made it through all the checks, this DIMM pair is usable
+ dimm_mask |= (1 << i) | (1 << (MAX_DIMM_SOCKETS_PER_CHANNEL + i));
+ break;
+ }
+#endif
+ }
- /* double because I have 2 channels */
- sz.side1++;
+ return dimm_mask;
+}
+
+/*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
+/* SPD (SERIAL PRESENCE DETECT) FUNCTIONS */
+/**********************************************************************************/
+
+//----------------------------------------------------------------------------------
+// Function: do_ram_command
+// Parameters:
+// command - specifies the command to be sent to the DIMMs:
+// RAM_COMMAND_NOP - No Operation
+// RAM_COMMAND_PRECHARGE - Precharge all banks
+// RAM_COMMAND_MRS - Load Mode Register
+// RAM_COMMAND_EMRS - Load Extended Mode Register
+// RAM_COMMAND_CBR - Auto Refresh ("CAS-before-RAS")
+// RAM_COMMAND_NORMAL - Normal operation
+// jedec_mode_bits - for mode register set & extended mode register set
+// commands, bits 0-12 contain the register value in JEDEC format.
+// Return Value: None
+// Description: Send the specified command to all DIMMs.
+//
+static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits)
+{
+ int i;
+ uint32_t dram_controller_mode;
+ uint8_t dimm_start_64M_multiple = 0;
+ uint16_t e7501_mode_bits = jedec_mode_bits;
+
+ // Configure the RAM command
+ dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC);
+ dram_controller_mode &= 0xFFFFFF8F;
+ dram_controller_mode |= command;
+ pci_write_config32(PCI_DEV(0, 0, 0), DRC, dram_controller_mode);
+
+ // RAM_COMMAND_NORMAL is an exception.
+ // It affects only the memory controller and does not need to be "sent" to the DIMMs.
+
+ if (command != RAM_COMMAND_NORMAL) {
- /* Convert to the format needed for the DRA register */
- sz.side1-=14;
+ // Send the command to all DIMMs by accessing a memory location within each
+ // NOTE: for mode select commands, some of the location address bits
+ // are part of the command
- /* Place in the %ebp the dra place holder */ //i
- dword |= sz.side1<<(i<<3);
-
- /* Test to see if the second side is present */
+ // Map JEDEC mode bits to E7501
+ if (command == RAM_COMMAND_MRS) {
+ // Host address lines [15:5] map to DIMM address lines [12:11, 9:1]
+ // The E7501 hard-sets DIMM address lines 10 & 0 to zero
- if( sz.side2 !=0) {
-
- /* Test for a valid dimm width */
- if((sz.side2 <15) || (sz.side2>18) ) {
- print_err("unsupported page size\r\n");
- }
+ ASSERT(!(jedec_mode_bits & 0x0401));
- /* double because I have 2 channels */
- sz.side2++;
+ e7501_mode_bits = ((jedec_mode_bits & 0x1800) << (15 - 12)) | // JEDEC bits 11-12 move to bits 14-15
+ ((jedec_mode_bits & 0x03FE) << (13 - 9)); // JEDEC bits 1-9 move to bits 5-13
- /* Convert to the format needed for the DRA register */
- sz.side2-=14;
+ } else if (command == RAM_COMMAND_EMRS) {
+ // Host address lines [15:3] map to DIMM address lines [12:0]
+ e7501_mode_bits = jedec_mode_bits <<= 3;
+ } else
+ ASSERT(jedec_mode_bits == 0);
- /* Place in the %ebp the dra place holder */ //i
- dword |= sz.side2<<((i<<3) + 4 );
+ dimm_start_64M_multiple = 0;
+ for (i = 0; i < (MAX_NUM_CHANNELS * MAX_DIMM_SOCKETS_PER_CHANNEL); ++i) {
+
+ uint8_t dimm_end_64M_multiple =
+ pci_read_config8(PCI_DEV(0, 0, 0), DRB_ROW_0 + i);
+ if (dimm_end_64M_multiple > dimm_start_64M_multiple) {
+
+ // This code assumes DRAM row boundaries are all set below 4 GB
+ // NOTE: 0x40 * 64 MB == 4 GB
+ ASSERT(dimm_start_64M_multiple < 0x40);
+
+ // NOTE: 2^26 == 64 MB
+
+ uint32_t dimm_start_address =
+ dimm_start_64M_multiple << 26;
+
+ RAM_DEBUG_MESSAGE(" Sending RAM command to 0x");
+ RAM_DEBUG_HEX32(dimm_start_address + e7501_mode_bits);
+ RAM_DEBUG_MESSAGE("\n");
+
+ read32(dimm_start_address + e7501_mode_bits);
+
+ // Set the start of the next DIMM
+ dimm_start_64M_multiple =
+ dimm_end_64M_multiple;
}
}
+ }
+}
- /* Now add the SDRAM chip width to the DRA */
- struct dimm_width wd;
- wd = sdram_spd_get_width(ctrl->channel0[i]);
+//----------------------------------------------------------------------------------
+// Function: set_ram_mode
+// Parameters: jedec_mode_bits - for mode register set & extended mode register set
+// commands, bits 0-12 contain the register value in JEDEC format.
+// Return Value: None
+// Description: Set the mode register of all DIMMs. The proper CAS# latency
+// setting is added to the mode bits specified by the caller.
+//
+static void set_ram_mode(uint16_t jedec_mode_bits)
+{
+ ASSERT(!(jedec_mode_bits & SDRAM_CAS_MASK));
-#if DEBUG_RAM_CONFIG
- print_debug("width =");
- print_debug_hex32(wd.side1);
- print_debug(" ");
- print_debug_hex32(wd.side2);
- print_debug("\r\n");
-#endif
-
- if(wd.side1 == 0) continue;
- if(wd.side1 == 4) {
- /* Enable an x4 device */
- dword |= 0x08 << (i<<3);
- }
+ uint32_t dram_cas_latency =
+ pci_read_config32(PCI_DEV(0, 0, 0), DRT) & DRT_CAS_MASK;
- if(wd.side2 == 0) continue;
- if(wd.side2 == 4) {
- /* Enable an x4 device */
- dword |= 0x08 << ((i<<3 ) + 4);
- }
-
- /* go to the next DIMM */
- }
+ switch (dram_cas_latency) {
+ case DRT_CAS_2_5:
+ jedec_mode_bits |= SDRAM_CAS_2_5;
+ break;
- /* Write the new row attributes register */
- pci_write_config32(ctrl->d0, 0x70, dword);
+ case DRT_CAS_2_0:
+ jedec_mode_bits |= SDRAM_CAS_2_0;
+ break;
- return dimm_mask;
+ default:
+ BUG();
+ break;
+ }
-}
-#if 0
- /*
- * Routine: sdram_read_paired_byte
- * Arguments: %esp return address
- * %bl device on the smbus to read from
- * %bh address on the smbus to read
- * Results:
- * zf clear
- * byte read in %al
- * On Error:
- * zf set
- * %eax trashed
- *
- * Preserved: %ebx, %esi, %edi
- *
- * Trashed: %eax, %ecx, %edx, %ebp, %esp, %eflags
- * Used: %eax, %ebx, %ecx, %edx, %esp, %eflags
- *
- * Effects: Reads two spd bytes from both ram channesl
- * and errors if they are not equal.
- * It then returns the equal result.
- */
-static spd_read_paired_byte () {
- movl %esp, %ebp
- CALLSP(smbus_read_byte)
- setnz %cl
- movb %al, %ch
- addb $(SMBUS_MEM_CHANNEL_OFF), %bl
- CALLSP(smbus_read_byte)
- movb %ch, %ah
- setnz %ch
- subb $(SMBUS_MEM_CHANNEL_OFF), %bl
-
- /* See if dimms on both sides are equally present */
- cmp %cl, %ch
- jne sdram_presence_mismatch
-
- /* Leave if I have no data */
- testb %cl, %cl
- jz spd_verify_byte_out
-
- /* Verify the data is identical */
- cmp %ah, %al
- jne sdram_value_mismatch
-
- /* Clear the zero flag */
- testb %cl, %cl
-spd_verify_byte_out:
- movl %ebp, %esp
- RETSP
+ do_ram_command(RAM_COMMAND_MRS, jedec_mode_bits);
}
- /*
- * Routine: spd_verify_dimms
- * Arguments: none
- * Results: none
- * Preserved: none
- * Trashed: %eax, %ebx, %ecx, %edx, %ebp, %esi, %edi, %esp, %eflags
- * Used: %eax, %ebx, %ecx, %edx, %ebp, %esi, %edi, %esp, %eflags
- *
- * Effects:
- * - Verify all interesting spd information
- * matches for both dimm channels.
- * - Additional error checks that can be easily done
- * here are computed as well, so I don't need to
- * worry about them later.
- */
-static spd_verify_dimms() {
- movl $(SMBUS_MEM_DEVICE_START), %ebx
-spd_verify_dimm:
- /* Verify this is DDR SDRAM */
- movb $2, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_verify_next_dimm
- cmpb $7, %al
- jne invalid_dimm_type
-
- /* Verify the row addresses */
- movb $3, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
- testb $0x0f, %al
- jz spd_invalid_data
-
- /* Column addresses */
- movb $4, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
- testb $0xf, %al
- jz spd_invalid_data
-
- /* Physical Banks */
- movb $5, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
- cmp $1, %al
- jb spd_invalid_data
- cmp $2, %al
- ja spd_invalid_data
-
- /* Module Data Width */
- movb $7, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
- cmpb $0, %al
- jne spd_invalid_data
-
- movb $6, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
- cmpb $64, %al
- je 1f
- cmpb $72, %al
- je 1f
- jmp spd_unsupported_data
-1:
-
- /* Cycle time at highest CAS latency CL=X */
- movb $9, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
-
- /* SDRAM type */
- movb $11, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
-
- /* Refresh Interval */
- movb $12, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
-
- /* SDRAM Width */
- movb $13, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
- andb $0x7f, %al
- cmpb $4, %al
- je 1f
- cmpb $8, %al
- je 1f
- jmp spd_unsupported_data
-1:
-
- /* Back-to-Back Random Column Accesses */
- movb $15, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
- testb %al, %al
- jz spd_invalid_data
- cmpb $4, %al
- ja spd_unsupported_data
-
- /* Burst Lengths */
- movb $16, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
- testb $(1<<2), %al
- jz spd_unsupported_data
-
- /* Logical Banks */
- movb $17, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
- testb %al, %al
- jz spd_invalid_data
-
- /* Supported CAS Latencies */
- movb $18, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
- testb $(1 << 1), %al /* CL 1.5 */
- jnz 1f
- testb $(1 << 2), %al /* CL 2.0 */
- jnz 1f
- testb $(1 << 3), %al /* CL 2.5 */
- jnz 1f
- jmp spd_unsupported_data
-1:
-
- /* Cycle time at Cas Latency (CLX - 0.5) */
- movb $23, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
-
- /* Cycle time at Cas Latency (CLX - 1.0) */
- movb $26, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
-
- /* tRP Row precharge time */
- movb $27, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
- testb $0xfc, %al
- jz spd_invalid_data
-
-
- /* tRCD RAS to CAS */
- movb $29, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
- testb $0xfc, %al
- jz spd_invalid_data
-
- /* tRAS Activate to Precharge */
- movb $30, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
- testb %al, %al
- jz spd_invalid_data
-
- /* Module Bank Density */
- movb $31, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
- testb $(1<<2), %al /* 16MB */
- jnz spd_unsupported_data
- testb $(1<<3), %al
- jnz spd_unsupported_data /* 32MB */
-
- /* Address and Command Hold Time After Clock */
- movb $33, %bh
- CALLSP(spd_read_paired_byte)
- jz spd_missing_data
-
-spd_verify_next_dimm:
- /* go to the next DIMM */
- addb $(SMBUS_MEM_DEVICE_INC), %bl /* increment the smbus device */
- cmpb $SMBUS_MEM_DEVICE_END, %bl
- jbe spd_verify_dimm
-spd_verify_dimms_out:
- RET_LABEL(spd_verify_dimms)
+/*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
+/* SDRAM CONFIGURATION FUNCTIONS */
+/**********************************************************************************/
+
+//----------------------------------------------------------------------------------
+// Function: configure_dimm_row_boundaries
+// Parameters:
+// dimm_log2_num_bits - log2(number of bits) for each side of the DIMM
+// total_dram_64M_multiple - total DRAM in the system (as a
+// multiple of 64 MB) for DIMMs < dimm_index
+// dimm_index - which DIMM pair is being processed
+// (0..MAX_DIMM_SOCKETS_PER_CHANNEL)
+// Return Value: New multiple of 64 MB total DRAM in the system
+// Description: Configure the E7501's DRAM Row Boundary registers for the memory
+// present in the specified DIMM.
+//
+static uint8_t configure_dimm_row_boundaries(struct dimm_size dimm_log2_num_bits, uint8_t total_dram_64M_multiple, unsigned dimm_index)
+{
+ int i;
+
+ ASSERT(dimm_index < MAX_DIMM_SOCKETS_PER_CHANNEL);
+
+ // DIMM sides must be at least 32 MB
+ ASSERT(dimm_log2_num_bits.side1 >= 28);
+ ASSERT((dimm_log2_num_bits.side2 == 0)
+ || (dimm_log2_num_bits.side2 >= 28));
+
+ // In dual-channel mode, we are called only once for each pair of DIMMs.
+ // Each time we process twice the capacity of a single DIMM.
+
+ // Convert single DIMM capacity to paired DIMM capacity
+ // (multiply by two ==> add 1 to log2)
+ dimm_log2_num_bits.side1++;
+ if (dimm_log2_num_bits.side2 > 0)
+ dimm_log2_num_bits.side2++;
+
+ // Add the capacity of side 1 this DIMM pair (as a multiple of 64 MB)
+ // to the total capacity of the system
+ // NOTE: 64 MB == 512 Mb, and log2(512 Mb) == 29
+
+ total_dram_64M_multiple += (1 << (dimm_log2_num_bits.side1 - 29));
+
+ // Configure the boundary address for the row on side 1
+ pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_0 + (dimm_index << 1),
+ total_dram_64M_multiple);
+
+ // If the DIMMs are double-sided, add the capacity of side 2 this DIMM pair
+ // (as a multiple of 64 MB) to the total capacity of the system
+ if (dimm_log2_num_bits.side2 >= 29)
+ total_dram_64M_multiple +=
+ (1 << (dimm_log2_num_bits.side2 - 29));
+
+ // Configure the boundary address for the row (if any) on side 2
+ pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_1 + (dimm_index << 1),
+ total_dram_64M_multiple);
+
+ // Update boundaries for rows subsequent to these.
+ // These settings will be overridden by a subsequent call if a populated physical slot exists
+
+ for (i = dimm_index + 1; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
+ pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_0 + (i << 1),
+ total_dram_64M_multiple);
+ pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_1 + (i << 1),
+ total_dram_64M_multiple);
+ }
+
+ return total_dram_64M_multiple;
}
-#endif
-#define spd_pre_init "Reading SPD data...\r\n"
-#define spd_pre_set "setting based on SPD data...\r\n"
-#define spd_post_init "done\r\n"
-
-
-static const uint32_t refresh_rate_rank[]= {
- /* Refresh rates ordered from most conservative (lowest)
- * to most agressive (highest)
- * disabled 0 -> rank 3
- * 15.6usec 1 -> rank 1
- * 7.8 usec 2 -> rank 0
- * 64usec 3 -> rank 2
- */
- 3, 1, 0, 2 };
-static const uint32_t refresh_rate_index[] = {
- /* Map the spd refresh rates to memory controller settings
- * 15.625us -> 15.6us
- * 3.9us -> err
- * 7.8us -> 7.8us
- * 31.3s -> 15.6us
- * 62.5us -> 15.6us
- * 125us -> 64us
- */
- 1, 0xff, 2, 1, 1, 3
-};
-#define MAX_SPD_REFRESH_RATE 5
-
-static long spd_set_dram_controller_mode (const struct mem_controller *ctrl, long dimm_mask) {
-
- int i;
- uint32_t dword;
- int value;
- uint32_t ecx;
- uint32_t edx;
-
- /* Read the inititial state */
- dword = pci_read_config32(ctrl->d0, 0x7c);
-
-#if 0
- /* Test if ECC cmos option is enabled */
- movb $RTC_BOOT_BYTE, %al
- outb %al, $0x70
- inb $0x71, %al
- testb $(1<<2), %al
- jnz 1f
- /* Clear the ecc enable */
- andl $~(3 << 20), %esi
-1:
-#endif
+//----------------------------------------------------------------------------------
+// Function: configure_e7501_ram_addresses
+// Parameters: ctrl - PCI addresses of memory controller functions, and
+// SMBus addresses of DIMM slots on the mainboard
+// dimm_mask - bitmask of populated DIMMs on the board - see
+// spd_get_supported_dimms()
+// Return Value: None
+// Description: Program the E7501's DRAM row boundary addresses and its Top Of
+// Low Memory (TOLM). If necessary, set up a remap window so we
+// don't waste DRAM that ordinarily would lie behind addresses
+// reserved for memory-mapped I/O.
+//
+static void configure_e7501_ram_addresses(const struct mem_controller
+ *ctrl, uint8_t dimm_mask)
+{
+ int i;
+ uint8_t total_dram_64M_multiple = 0;
- /* Walk through all dimms and find the interesection of the support
- * for ecc sdram and refresh rates
- */
+ // Configure the E7501's DRAM row boundaries
+ // Start by zeroing out the temporary initial configuration
+ pci_write_config32(PCI_DEV(0, 0, 0), DRB_ROW_0, 0);
+ pci_write_config32(PCI_DEV(0, 0, 0), DRB_ROW_4, 0);
-
- for(i = 0; i < DIMM_SOCKETS; i++) {
- if (!(dimm_mask & (1 << i))) {
- continue;
- }
- /* Test to see if I have ecc sdram */
- value = spd_read_byte(ctrl->channel0[i], 11); /* SDRAM type */
- if(value < 0) continue;
- if(value !=2 ) {
- /* Clear the ecc enable */
- dword &= ~(3 << 20);
- }
- value = spd_read_byte(ctrl->channel0[i], 12); /* SDRAM refresh rate */
- if(value < 0 ) continue;
- value &= 0x7f;
- if(value > MAX_SPD_REFRESH_RATE) { print_err("unsupported refresh rate\r\n");}
-// if(value == 0xff) { print_err("unsupported refresh rate\r\n");}
-
- ecx = refresh_rate_index[value];
-
- /* Isolate the old refresh rate setting */
- /* Load the refresh rate ranks */
- edx = refresh_rate_rank[(dword >> 8) & 3]<<8;
- edx |= refresh_rate_rank[ecx] & 0xff;
-
- /* See if the new refresh rate is more conservative than the old
- * refresh rate setting. (Lower ranks are more conservative)
- */
- if((edx & 0xff)< ((edx >> 8) & 0xff) ) {
- /* Clear the old refresh rate */
- dword &= ~(3<<8);
- /* Move in the new refresh rate */
- dword |= (ecx<<8);
- }
-
- value = spd_read_byte(ctrl->channel0[i], 33); /* Address and command hold time after clock */
- if(value < 0) continue;
- if(value >= 0xa0) { /* At 133Mhz this constant should be 0x75 */
- dword &= ~(1<<16); /* Use two clock cyles instead of one */
+ for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
+
+ uint16_t dimm_socket_address = ctrl->channel0[i];
+ struct dimm_size sz;
+
+ if (!(dimm_mask & (1 << i)))
+ continue; // This DIMM not present
+
+ sz = spd_get_dimm_size(dimm_socket_address);
+
+ RAM_DEBUG_MESSAGE("dimm size =");
+ RAM_DEBUG_HEX32(sz.side1);
+ RAM_DEBUG_MESSAGE(" ");
+ RAM_DEBUG_HEX32(sz.side2);
+ RAM_DEBUG_MESSAGE("\n");
+
+ if (sz.side1 == 0)
+ die("Bad SPD value\n");
+
+ total_dram_64M_multiple =
+ configure_dimm_row_boundaries(sz, total_dram_64M_multiple, i);
+ }
+
+ // Configure the Top Of Low Memory (TOLM) in the E7501
+ // This address must be a multiple of 128 MB that is less than 4 GB.
+ // NOTE: 16-bit wide TOLM register stores only the highest 5 bits of a 32-bit address
+ // in the highest 5 bits.
+
+ // We set TOLM to the smaller of 0xC0000000 (3 GB) or the total DRAM in the system.
+ // This reserves addresses from 0xC0000000 - 0xFFFFFFFF for non-DRAM purposes
+ // such as flash and memory-mapped I/O.
+
+ // If there is more than 3 GB of DRAM, we define a remap window which
+ // makes the DRAM "behind" the reserved region available above the top of physical
+ // memory.
+
+ // NOTE: 0xC0000000 / (64 MB) == 0x30
+
+ if (total_dram_64M_multiple <= 0x30) {
+
+ // <= 3 GB total RAM
+
+ /* I should really adjust all of this in C after I have resources
+ * to all of the pci devices.
+ */
+
+ // Round up to 128MB granularity
+ // SJM: Is "missing" 64 MB of memory a potential issue? Should this round down?
+
+ uint8_t total_dram_128M_multiple =
+ (total_dram_64M_multiple + 1) >> 1;
+
+ // Convert to high 16 bits of address
+ uint16_t top_of_low_memory =
+ total_dram_128M_multiple << 11;
+
+ pci_write_config16(PCI_DEV(0, 0, 0), TOLM,
+ top_of_low_memory);
+
+ } else {
+
+ // > 3 GB total RAM
+
+ // Set defaults for > 4 GB DRAM, i.e. remap a 1 GB (= 0x10 * 64 MB) range of memory
+ uint16_t remap_base = total_dram_64M_multiple; // A[25:0] == 0
+ uint16_t remap_limit = total_dram_64M_multiple + 0x10 - 1; // A[25:0] == 0xF
+
+ // Put TOLM at 3 GB
+
+ pci_write_config16(PCI_DEV(0, 0, 0), TOLM, 0xc000);
+
+ // Define a remap window to make the RAM that would appear from 3 GB - 4 GB
+ // visible just beyond 4 GB or the end of physical memory, whichever is larger
+ // NOTE: 16-bit wide REMAP registers store only the highest 10 bits of a 36-bit address,
+ // (i.e. a multiple of 64 MB) in the lowest 10 bits.
+ // NOTE: 0x100000000 / (64 MB) == 0x40
+
+ if (total_dram_64M_multiple < 0x40) {
+ remap_base = 0x40; // 0x100000000
+ remap_limit =
+ 0x40 + (total_dram_64M_multiple - 0x30) - 1;
}
-
- /* go to the next DIMM */
+
+ pci_write_config16(PCI_DEV(0, 0, 0), REMAPBASE,
+ remap_base);
+ pci_write_config16(PCI_DEV(0, 0, 0), REMAPLIMIT,
+ remap_limit);
}
+}
- /* Now write the controller mode */
- pci_write_config32(ctrl->d0, 0x7c, dword);
-
- return dimm_mask;
+//----------------------------------------------------------------------------------
+// Function: initialize_ecc
+// Parameters: None
+// Return Value: None
+// Description: If we're configured to use ECC, initialize the SDRAM and
+// clear the E7501's ECC error flags.
+//
+static void initialize_ecc(void)
+{
+ uint32_t dram_controller_mode;
+
+ /* Test to see if ECC support is enabled */
+ dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC);
+ dram_controller_mode >>= 20;
+ dram_controller_mode &= 3;
+ if (dram_controller_mode == 2) {
+
+ uint8_t byte;
+
+ RAM_DEBUG_MESSAGE("Initializing ECC state...\n");
+ /* Initialize ECC bits , use ECC zero mode (new to 7501) */
+ pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, 0x06);
+ pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, 0x07);
+
+ // Wait for scrub cycle to complete
+ do {
+ byte =
+ pci_read_config8(PCI_DEV(0, 0, 0), MCHCFGNS);
+ } while ((byte & 0x08) == 0);
+
+ pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, byte & 0xfc);
+ RAM_DEBUG_MESSAGE("ECC state initialized.\n");
+
+ /* Clear the ECC error bits */
+ pci_write_config8(PCI_DEV(0, 0, 1), DRAM_FERR, 0x03);
+ pci_write_config8(PCI_DEV(0, 0, 1), DRAM_NERR, 0x03);
+
+ // Clear DRAM Interface error bits (write-one-clear)
+ pci_write_config32(PCI_DEV(0, 0, 1), FERR_GLOBAL, 1 << 18);
+ pci_write_config32(PCI_DEV(0, 0, 1), NERR_GLOBAL, 1 << 18);
+
+ // Start normal ECC scrub
+ pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, 5);
+ }
}
-static long spd_enable_clocks(const struct mem_controller *ctrl, long dimm_mask)
+
+//----------------------------------------------------------------------------------
+// Function: configure_e7501_dram_timing
+// Parameters: ctrl - PCI addresses of memory controller functions, and
+// SMBus addresses of DIMM slots on the mainboard
+// dimm_mask - bitmask of populated DIMMs on the board - see
+// spd_get_supported_dimms()
+// Return Value: None
+// Description: Program the DRAM Timing register of the E7501 (except for CAS#
+// latency, which is assumed to have been programmed already), based
+// on the parameters of the various installed DIMMs.
+//
+static void configure_e7501_dram_timing(const struct mem_controller *ctrl,
+ uint8_t dimm_mask)
{
- int i;
- uint32_t dword;
+ int i;
+ uint32_t dram_timing;
int value;
+ uint8_t slowest_row_precharge = 0;
+ uint8_t slowest_ras_cas_delay = 0;
+ uint8_t slowest_active_to_precharge_delay = 0;
+ uint32_t current_cas_latency =
+ pci_read_config32(PCI_DEV(0, 0, 0), DRT) & DRT_CAS_MASK;
+
+ // CAS# latency must be programmed beforehand
+ ASSERT((current_cas_latency == DRT_CAS_2_0)
+ || (current_cas_latency == DRT_CAS_2_5));
+
+ // Each timing parameter is determined by the slowest DIMM
+
+ for (i = 0; i < MAX_DIMM_SOCKETS; i++) {
+ uint16_t dimm_socket_address;
+
+ if (!(dimm_mask & (1 << i)))
+ continue; // This DIMM not present
+
+ if (i < MAX_DIMM_SOCKETS_PER_CHANNEL)
+ dimm_socket_address = ctrl->channel0[i];
+ else
+ dimm_socket_address =
+ ctrl->channel1[i - MAX_DIMM_SOCKETS_PER_CHANNEL];
+
+ value =
+ spd_read_byte(dimm_socket_address,
+ SPD_MIN_ROW_PRECHARGE_TIME);
+ if (value < 0)
+ goto hw_err;
+ if (value > slowest_row_precharge)
+ slowest_row_precharge = value;
+
+ value =
+ spd_read_byte(dimm_socket_address,
+ SPD_MIN_RAS_TO_CAS_DELAY);
+ if (value < 0)
+ goto hw_err;
+ if (value > slowest_ras_cas_delay)
+ slowest_ras_cas_delay = value;
+
+ value =
+ spd_read_byte(dimm_socket_address,
+ SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
+ if (value < 0)
+ goto hw_err;
+ if (value > slowest_active_to_precharge_delay)
+ slowest_active_to_precharge_delay = value;
+ }
- /* Read the inititial state */
- dword = pci_read_config32(ctrl->d0, 0x8c);
-#if 0
-# Intel clears top bit here, should we?
-# No the default is on and for normal timming it should be on. Tom Z
- andl $0x7f, %esi
-#endif
+ // NOTE for timing parameters:
+ // At 133 MHz, 1 clock == 7.52 ns
-
- for(i = 0; i < DIMM_SOCKETS; i++) {
- if (!(dimm_mask & (1 << i))) {
- continue;
- }
- /* Read any spd byte to see if the dimm is present */
- value = spd_read_byte(ctrl->channel0[i], 5); /* Physical Banks */
- if(value < 0) continue;
-
- dword &= ~(1<<i);
- }
-
- pci_write_config32(ctrl->d0, 0x8c, dword);
-
- return dimm_mask;
-}
+ /* Read the initial state */
+ dram_timing = pci_read_config32(PCI_DEV(0, 0, 0), DRT);
-static const uint16_t cas_latency_80[] = {
- /* For cas latency 2.0 0x01 works and until I see a large test sample
- * I am not prepared to change this value, to the intel recommended value
- * of 0x0d. Eric Biederman
- */
- /* The E7501 requires b1 rather than 01 for CAS2 or memory will be hosed
- * CAS 1.5 is claimed to be unsupported, will try to test that
- * will need to determine correct values for other CAS values
- * (perhaps b5, b1, b6?)
- * Steven James 02/06/2003
- */
-
-//# .byte 0x05, 0x01, 0x06
-//# .byte 0xb5, 0xb1, 0xb6
- 0x0, 0x0bb1, 0x0662 /* RCVEN */
-};
-static const uint16_t cas_latency_80_4dimms[] = {
- 0x0, 0x0bb1, 0x0882
-};
+ /* Trp */
+ // E7501 supports only 2 or 3 clocks for tRP
+ if (slowest_row_precharge > ((22 << 2) | (2 << 0)))
+ die("unsupported DIMM tRP"); // > 22.5 ns: 4 or more clocks
+ else if (slowest_row_precharge > (15 << 2))
+ dram_timing &= ~(1 << 0); // > 15.0 ns: 3 clocks
+ else
+ dram_timing |= (1 << 0); // <= 15.0 ns: 2 clocks
-static const uint8_t cas_latency_78[] = {
- DRT_CAS_1_5, DRT_CAS_2_0, DRT_CAS_2_5
-};
+ /* Trcd */
+
+ // E7501 supports only 2 or 3 clocks for tRCD
+ // Use the same value for both read & write
+ dram_timing &= ~((1 << 3) | (3 << 1));
+ if (slowest_ras_cas_delay > ((22 << 2) | (2 << 0)))
+ die("unsupported DIMM tRCD"); // > 22.5 ns: 4 or more clocks
+ else if (slowest_ras_cas_delay > (15 << 2))
+ dram_timing |= (2 << 1); // > 15.0 ns: 3 clocks
+ else
+ dram_timing |= ((1 << 3) | (3 << 1)); // <= 15.0 ns: 2 clocks
+
+ /* Tras */
+
+ // E7501 supports only 5, 6, or 7 clocks for tRAS
+ // 5 clocks ~= 37.6 ns, 6 clocks ~= 45.1 ns, 7 clocks ~= 52.6 ns
+ dram_timing &= ~(3 << 9);
+
+ if (slowest_active_to_precharge_delay > 52)
+ die("unsupported DIMM tRAS"); // > 52 ns: 8 or more clocks
+ else if (slowest_active_to_precharge_delay > 45)
+ dram_timing |= (0 << 9); // 46-52 ns: 7 clocks
+ else if (slowest_active_to_precharge_delay > 37)
+ dram_timing |= (1 << 9); // 38-45 ns: 6 clocks
+ else
+ dram_timing |= (2 << 9); // < 38 ns: 5 clocks
+
+ /* Trd */
+
+ /* Set to a 7 clock read delay. This is for 133Mhz
+ * with a CAS latency of 2.5 if 2.0 a 6 clock
+ * delay is good */
+
+ dram_timing &= ~(7 << 24); // 7 clocks
+ if (current_cas_latency == DRT_CAS_2_0)
+ dram_timing |= (1 << 24); // 6 clocks
-static long spd_set_cas_latency(const struct mem_controller *ctrl, long dimm_mask) {
- /* Walk through all dimms and find the interesection of the
- * supported cas latencies.
+ /*
+ * Back to Back Read-Write Turn Around
*/
- int i;
- /* Initially allow cas latencies 2.5, 2.0
- * which the chipset supports.
- */
- uint32_t dword = (1<<3)| (1<<2);// esi
- uint32_t edi;
- uint32_t ecx;
- unsigned device;
+ /* Set to a 5 clock back to back read to write turn around.
+ * 4 is a good delay if the CAS latency is 2.0 */
+
+ dram_timing &= ~(1 << 28); // 5 clocks
+ if (current_cas_latency == DRT_CAS_2_0)
+ dram_timing |= (1 << 28); // 4 clocks
+
+ pci_write_config32(PCI_DEV(0, 0, 0), DRT, dram_timing);
+
+ return;
+
+ hw_err:
+ die(SPD_ERROR);
+}
+
+//----------------------------------------------------------------------------------
+// Function: configure_e7501_cas_latency
+// Parameters: ctrl - PCI addresses of memory controller functions, and
+// SMBus addresses of DIMM slots on the mainboard
+// dimm_mask - bitmask of populated DIMMs on the board - see
+// spd_get_supported_dimms()
+// Return Value: None
+// Description: Determine the shortest CAS# latency that the E7501 and all DIMMs
+// have in common, and program the E7501 to use it.
+//
+static void configure_e7501_cas_latency(const struct mem_controller *ctrl,
+ uint8_t dimm_mask)
+{
+ int i;
int value;
- uint8_t byte;
- uint16_t word;
+ uint32_t dram_timing;
+ uint16_t maybe_dram_read_timing;
+ uint32_t dword;
-
- for(i = 0; i < DIMM_SOCKETS; i++) {
- if (!(dimm_mask & (1 << i))) {
- continue;
- }
- value = spd_read_byte(ctrl->channel0[i], 18);
- if(value < 0) continue;
- /* Find the highest supported cas latency */
- ecx = log2(value & 0xff);
- edi = (1<< ecx);
-
- /* Remember the supported cas latencies */
- ecx = (value & 0xff);
-
- /* Verify each cas latency at 133Mhz */
- /* Verify slowest/highest CAS latency */
- value = spd_read_byte(ctrl->channel0[i], 9);
- if(value < 0 ) continue;
- if(value > 0x75 ) {
- /* The bus is too fast so we cannot support this case latency */
- ecx &= ~edi;
- }
+ // CAS# latency bitmasks in SPD_ACCEPTABLE_CAS_LATENCIES format
+ // NOTE: E7501 supports only 2.0 and 2.5
+ uint32_t system_compatible_cas_latencies =
+ SPD_CAS_LATENCY_2_0 | SPD_CAS_LATENCY_2_5;
+ uint32_t current_cas_latency;
+ uint32_t dimm_compatible_cas_latencies;
- /* Verify the highest CAS latency - 0.5 clocks */
- edi >>= 1;
- if(edi != 0) {
- value = spd_read_byte(ctrl->channel0[i], 23);
- if(value < 0 ) continue;
- if(value > 0x75) {
- /* The bus is too fast so we cannot support this cas latency */
- ecx &= ~edi;
- }
- }
+ for (i = 0; i < MAX_DIMM_SOCKETS; i++) {
- /* Verify the highest CAS latency - 1.0 clocks */
- edi >>=1;
- if(edi !=0) {
- value = spd_read_byte(ctrl->channel0[i], 25);
- if(value < 0 ) continue;
- if(value > 0x75) {
- /* The bus is too fast so we cannot support this cas latency */
- ecx &= ~edi;
- }
+ uint16_t dimm_socket_address;
+
+ if (!(dimm_mask & (1 << i)))
+ continue; // This DIMM not usable
+
+ if (i < MAX_DIMM_SOCKETS_PER_CHANNEL)
+ dimm_socket_address = ctrl->channel0[i];
+ else
+ dimm_socket_address =
+ ctrl->channel1[i - MAX_DIMM_SOCKETS_PER_CHANNEL];
+
+ value =
+ spd_read_byte(dimm_socket_address,
+ SPD_ACCEPTABLE_CAS_LATENCIES);
+ if (value < 0)
+ goto hw_err;
+
+ dimm_compatible_cas_latencies = value & 0x7f; // Start with all supported by DIMM
+ current_cas_latency = 1 << log2(dimm_compatible_cas_latencies); // Max supported by DIMM
+
+ // Can we support the highest CAS# latency?
+
+ value =
+ spd_read_byte(dimm_socket_address,
+ SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
+ if (value < 0)
+ goto hw_err;
+
+ // NOTE: At 133 MHz, 1 clock == 7.52 ns
+ if (value > 0x75) {
+ // Our bus is too fast for this CAS# latency
+ // Remove it from the bitmask of those supported by the DIMM that are compatible
+ dimm_compatible_cas_latencies &= ~current_cas_latency;
+ }
+ // Can we support the next-highest CAS# latency (max - 0.5)?
+
+ current_cas_latency >>= 1;
+ if (current_cas_latency != 0) {
+ value =
+ spd_read_byte(dimm_socket_address,
+ SPD_SDRAM_CYCLE_TIME_2ND);
+ if (value < 0)
+ goto hw_err;
+ if (value > 0x75)
+ dimm_compatible_cas_latencies &=
+ ~current_cas_latency;
}
+ // Can we support the next-highest CAS# latency (max - 1.0)?
+ current_cas_latency >>= 1;
+ if (current_cas_latency != 0) {
+ value =
+ spd_read_byte(dimm_socket_address,
+ SPD_SDRAM_CYCLE_TIME_3RD);
+ if (value < 0)
+ goto hw_err;
+ if (value > 0x75)
+ dimm_compatible_cas_latencies &=
+ ~current_cas_latency;
+ }
+ // Restrict the system to CAS# latencies compatible with this DIMM
+ system_compatible_cas_latencies &=
+ dimm_compatible_cas_latencies;
- /* Now find which cas latencies are supported for the bus */
- dword &= ecx;
- /* go to the next DIMM */
+ /* go to the next DIMM */
}
/* After all of the arduous calculation setup with the fastest
* cas latency I can use.
*/
- value = __builtin_bsf(dword); // bsrl = log2 how about bsfl?
- if(value ==0 ) return -1;
- ecx = value -1;
- byte = pci_read_config8(ctrl->d0, 0x78);
- byte &= ~(DRT_CAS_MASK);
- byte |= cas_latency_78[ecx];
- pci_write_config8(ctrl->d0,0x78, byte);
+ dram_timing = pci_read_config32(PCI_DEV(0, 0, 0), DRT);
+ dram_timing &= ~(DRT_CAS_MASK);
+
+ maybe_dram_read_timing =
+ pci_read_config16(PCI_DEV(0, 0, 0), MAYBE_DRDCTL);
+ maybe_dram_read_timing &= 0xF00C;
+
+ if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_0) {
+ dram_timing |= DRT_CAS_2_0;
+ maybe_dram_read_timing |= 0xBB1;
+ } else if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_5) {
+
+ uint32_t dram_row_attributes =
+ pci_read_config32(PCI_DEV(0, 0, 0), DRA);
+
+ dram_timing |= DRT_CAS_2_5;
+
+ // At CAS# 2.5, DRAM Read Timing (if that's what it its) appears to need a slightly
+ // different value if all DIMM slots are populated
+
+ if ((dram_row_attributes & 0xff)
+ && (dram_row_attributes & 0xff00)
+ && (dram_row_attributes & 0xff0000)
+ && (dram_row_attributes & 0xff000000)) {
+
+ // All slots populated
+ maybe_dram_read_timing |= 0x0882;
+ } else {
+ // Some unpopulated slots
+ maybe_dram_read_timing |= 0x0662;
+ }
+ } else
+ die("No CAS# latencies compatible with all DIMMs!!\n");
+
+ pci_write_config32(PCI_DEV(0, 0, 0), DRT, dram_timing);
/* set master DLL reset */
- dword = pci_read_config32(ctrl->d0, 0x88);
- dword |= (1<<26);
-
- /* the rest of the references are words */
-// ecx<<=1; // don't need shift left, because we already define that in u16 array
- pci_write_config32(ctrl->d0, 0x88, dword);
-
-
- dword &= 0x0c0000ff; /* patch try register 88 is undocumented tnz */
+ dword = pci_read_config32(PCI_DEV(0, 0, 0), 0x88);
+ dword |= (1 << 26);
+ pci_write_config32(PCI_DEV(0, 0, 0), 0x88, dword);
+
+ dword &= 0x0c0007ff; /* patch try register 88 is undocumented tnz */
dword |= 0xd2109800;
- pci_write_config32(ctrl->d0, 0x88, dword);
-
- word = pci_read_config16(ctrl->d0, 0x80);
- word &= ~(0x0fff);
- word |= cas_latency_80[ecx];
-
- dword = pci_read_config32(ctrl->d0, 0x70);
-
- if((dword & 0xff) !=0 ) {
- dword >>=8;
- if((dword & 0xff)!=0) {
- dword >>=8;
- if((dword & 0xff)!=0) {
- dword >>= 8;
- if( (dword & 0xff)!=0) {
- word &=~(0x0fff); /* we have dimms in all 4 slots */
- word |=cas_latency_80_4dimms[ecx];
- }
- }
- }
- }
-
- pci_write_config16(ctrl->d0, 0x80, word);
-
- dword = pci_read_config32(ctrl->d0, 0x88); /* reset master DLL reset */
- dword &= ~(1<<26);
- pci_write_config32(ctrl->d0, 0x88, dword);
-
- RAM_RESET_DDR_PTR(ctrl);
+ pci_write_config32(PCI_DEV(0, 0, 0), 0x88, dword);
- return dimm_mask;
+ pci_write_config16(PCI_DEV(0, 0, 0), MAYBE_DRDCTL,
+ maybe_dram_read_timing);
+ dword = pci_read_config32(PCI_DEV(0, 0, 0), 0x88); /* reset master DLL reset */
+ dword &= ~(1 << 26);
+ pci_write_config32(PCI_DEV(0, 0, 0), 0x88, dword);
+
+ return;
+
+ hw_err:
+ die(SPD_ERROR);
}
-static long spd_set_dram_timing(const struct mem_controller *ctrl, long dimm_mask) {
- /* Walk through all dimms and find the interesection of the
- * supported dram timings.
+//----------------------------------------------------------------------------------
+// Function: configure_e7501_dram_controller_mode
+// Parameters: ctrl - PCI addresses of memory controller functions, and
+// SMBus addresses of DIMM slots on the mainboard
+// dimm_mask - bitmask of populated DIMMs on the board - see
+// spd_get_supported_dimms()
+// Return Value: None
+// Description: Configure the refresh interval so that we refresh no more often
+// than required by the "most needy" DIMM. Also disable ECC if any
+// of the DIMMs don't support it.
+//
+static void configure_e7501_dram_controller_mode(const struct
+ mem_controller *ctrl,
+ uint8_t dimm_mask)
+{
+ int i;
+
+ // Initial settings
+ uint32_t controller_mode =
+ pci_read_config32(PCI_DEV(0, 0, 0), DRC);
+ uint32_t system_refresh_mode = (controller_mode >> 8) & 7;
+
+ // Code below assumes that most aggressive settings are in
+ // force when we are called, either via E7501 reset defaults
+ // or by sdram_set_registers():
+ // - ECC enabled
+ // - No refresh
+
+ ASSERT((controller_mode & (3 << 20)) == (2 << 20)); // ECC
+ ASSERT(!(controller_mode & (7 << 8))); // Refresh
+
+ /* Walk through _all_ dimms and find the least-common denominator for:
+ * - ECC support
+ * - refresh rates
*/
- int i;
- uint32_t dword;
- int value;
+ for (i = 0; i < MAX_DIMM_SOCKETS; i++) {
+
+ uint32_t dimm_refresh_mode;
+ int value;
+ uint16_t dimm_socket_address;
- /* Read the inititial state */
- dword = pci_read_config32(ctrl->d0, 0x78);
-#if 0
-# Intel clears top bit here, should we?
-# No the default is on and for normal timming it should be on. Tom Z
- andl $0x7f, %esi
-#endif
-
-
- for(i = 0; i < DIMM_SOCKETS; i++) {
if (!(dimm_mask & (1 << i))) {
- continue;
- }
- /* Trp */
- value = spd_read_byte(ctrl->channel0[i], 27);
- if(value < 0) continue;
- if(value > (15<<2)) {
- /* At 133Mhz if row precharge time is above than 15ns than we
- * need 3 clocks not 2 clocks.
- */
- dword &= ~(1<<0);
+ continue; // This DIMM not usable
}
- /* Trcd */
- value = spd_read_byte(ctrl->channel0[i],29);
- if(value < 0 ) continue;
- if(value > (15<<2)) {
- /* At 133Mhz if the Minimum ras to cas delay is about 15ns we
- * need 3 clocks not 2 clocks.
- */
- dword &= ~((1<<3)|(1<<1));
+
+ if (i < MAX_DIMM_SOCKETS_PER_CHANNEL)
+ dimm_socket_address = ctrl->channel0[i];
+ else
+ dimm_socket_address =
+ ctrl->channel1[i -
+ MAX_DIMM_SOCKETS_PER_CHANNEL];
+
+ // Disable ECC mode if any one of the DIMMs does not support ECC
+ // SJM: Should we just die here? E7501 datasheet says non-ECC DIMMs aren't supported.
+
+ value =
+ spd_read_byte(dimm_socket_address,
+ SPD_DIMM_CONFIG_TYPE);
+ die_on_spd_error(value);
+ if (value != ERROR_SCHEME_ECC) {
+ controller_mode &= ~(3 << 20);
}
- /* Tras */
- value = spd_read_byte(ctrl->channel0[i],30);
- if(value < 0 ) continue;
- /* Convert tRAS from ns to 133Mhz clock cycles */
- value <<=1; /* mult by 2 to make 7.5 15 */
- value += 15; /* Make certain we round up */
- value --;
- value &= 0xff; /* Clear the upper bits of eax */
- value /= 15;
-
- /* Don't even process small timings */
- if(value >5) {
- uint32_t tmp;
- /* Die if the value is to large */
- if(value>7) {
- die ("unsupported_rcd\r\n");
- }
- /* Convert to clocks - 5 */
- value -=5;
- /* Convert the existing value into clocks - 5 */
- tmp = (~((dword>>9) & 3) - 1) & 3;
- /* See if we need a slower timing */
- if(value > tmp ) {
- /* O.k. put in our slower timing */
- dword &= ~(3<<9);
- dword |= ((~(value + 1)) & 3)<<9 ;
- }
+
+ value = spd_read_byte(dimm_socket_address, SPD_REFRESH);
+ die_on_spd_error(value);
+ value &= 0x7f; // Mask off self-refresh bit
+ if (value > MAX_SPD_REFRESH_RATE) {
+ print_err("unsupported refresh rate\n");
+ continue;
}
-
- /* Trd */
- /* Set to a 7 clock read delay. This is for 133Mhz
- * with a CAS latency of 2.5 if 2.0 a 6 clock
- * delay is good */
- if( (pci_read_config8(ctrl->d0, 0x78) & 0x30) ==0 ){
- dword &= ~(7<<24); /* CAS latency is 2.5, make 7 clks */
+ // Get the appropriate E7501 refresh mode for this DIMM
+ dimm_refresh_mode = refresh_rate_map[value];
+ if (dimm_refresh_mode > 7) {
+ print_err("unsupported refresh rate\n");
+ continue;
}
-
- /*
- * Back to Back Read Turn Around
- */
- /* Set to a 3 clock back to back read turn around. This
- * is good for CAS latencys 2.5 and 2.0 */
- dword |= (1<<27);
- /*
- * Back to Back Read-Write Turn Around
- */
- /* Set to a 5 clock back to back read to write turn around.
- * 4 is a good delay if the CAS latency is 2.0 */
- if( ( pci_read_config8(ctrl->d0, 0x78) & (1<<4)) == 0) {
- dword &= ~(1<<28);
+ // If this DIMM requires more frequent refresh than others,
+ // update the system setting
+ if (refresh_frequency[dimm_refresh_mode] >
+ refresh_frequency[system_refresh_mode])
+ system_refresh_mode = dimm_refresh_mode;
+
+#ifdef SUSPICIOUS_LOOKING_CODE
+// SJM NOTE: This code doesn't look right. SPD values are an order of magnitude smaller
+// than the clock period of the memory controller. Also, no other northbridge
+// looks at SPD_CMD_SIGNAL_INPUT_HOLD_TIME.
+
+ // Switch to 2 clocks for address/command if required by any one of the DIMMs
+ // NOTE: At 133 MHz, 1 clock == 7.52 ns
+ value =
+ spd_read_byte(dimm_socket_address,
+ SPD_CMD_SIGNAL_INPUT_HOLD_TIME);
+ die_on_spd_error(value);
+ if (value >= 0xa0) { /* At 133MHz this constant should be 0x75 */
+ controller_mode &= ~(1 << 16); /* Use two clock cyles instead of one */
}
- /*
- * Back to Back Write-Read Turn Around
- */
- /* Set to a 2 clock back to back write to read turn around.
- * This is good for 2.5 and 2.0 CAS Latencies. */
- dword |= (1<<29);
- }
-
- pci_write_config32(ctrl->d0, 0x78, dword);
-
- return dimm_mask;
-
-}
-static unsigned int spd_detect_dimms(const struct mem_controller *ctrl)
-{
- unsigned dimm_mask;
- int i;
- dimm_mask = 0;
-#if DEBUG_RAM_CONFIG
- print_debug("spd_detect_dimms:\r\n");
-#endif
- for(i = 0; i < DIMM_SOCKETS; i++) {
- int byte;
- unsigned device;
-#if DEBUG_RAM_CONFIG
- print_debug_hex32(i);
- print_debug("\r\n");
#endif
- device = ctrl->channel0[i];
- if (device) {
- byte = spd_read_byte(ctrl->channel0[i], 2); /* Type */
- if (byte == 7) {
- dimm_mask |= (1 << i);
- }
- }
-#if 1
- device = ctrl->channel1[i];
- if (device) {
- byte = spd_read_byte(ctrl->channel1[i], 2);
- if (byte == 7) {
- dimm_mask |= (1 << (i + DIMM_SOCKETS));
- }
- }
-#endif
- }
-#if 1
- i = (dimm_mask>>DIMM_SOCKETS);
- if(i != (dimm_mask & ( (1<<DIMM_SOCKETS) - 1) ) ) {
- die("now we only support dual channel\r\n");
+
+ /* go to the next DIMM */
}
-#endif
+ controller_mode |= (system_refresh_mode << 8);
- return dimm_mask;
-}
+ // Configure the E7501
+ pci_write_config32(PCI_DEV(0, 0, 0), DRC, controller_mode);
+}
-static uint32_t set_dimm_size(const struct mem_controller *ctrl, struct dimm_size sz, uint32_t memsz, unsigned index)
+//----------------------------------------------------------------------------------
+// Function: configure_e7501_row_attributes
+// Parameters: ctrl - PCI addresses of memory controller functions, and
+// SMBus addresses of DIMM slots on the mainboard
+// dimm_mask - bitmask of populated DIMMs on the board - see
+// spd_get_supported_dimms()
+// Return Value: None
+// Description: Configure the E7501's DRAM Row Attributes (DRA) registers
+// based on DIMM parameters read via SPD. This tells the controller
+// the width of the SDRAM chips on each DIMM side (x4 or x8) and
+// the page size of each DIMM side (4, 8, 16, or 32 KB).
+//
+static void configure_e7501_row_attributes(const struct mem_controller
+ *ctrl, uint8_t dimm_mask)
{
- int i;
- uint32_t base0, base1;
- uint32_t dch;
- uint8_t byte;
+ int i;
+ uint32_t row_attributes = 0;
- /* Double the size if we are using dual channel memory */
-// if (is_dual_channel(ctrl)) {
- /* Since I have 2 identical channels double the sizes */
- sz.side1++ ;
- sz.side2++;
-// }
-
- if (sz.side1 != sz.side2) {
- sz.side2 = 0;
- }
-
- /* Make certain side1 of the dimm is at least 64MB */
- if (sz.side1 >= (25 + 4)) {
- memsz += (1 << (sz.side1 - (25 + 4)) ) ;
- }
- /* Write the size of side 1 of the dimm */
- byte = memsz;
- pci_write_config8(ctrl->d0, 0x60+(index<<1), byte);
-
- /* Make certain side2 of the dimm is at least 64MB */
- if (sz.side2 >= (25 + 4)) {
- memsz += (1 << (sz.side2 - (25 + 4)) ) ;
- }
-
- /* Write the size of side 2 of the dimm */
- byte = memsz;
- pci_write_config8(ctrl->d0, 0x61+(index<<1), byte);
-
- /* now, fill in DRBs where no physical slot exists */
-
- for(i=index+1;i<4;i++) {
- pci_write_config8(ctrl->d0, 0x60+(i<<1),byte);
- pci_write_config8(ctrl->d0, 0x61+(i<<1),byte);
-
- }
-
- return memsz;
+ for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
-}
-/* LAST_DRB_SLOT is a constant for any E7500 board */
-#define LAST_DRB_SLOT 0x67
+ uint16_t dimm_socket_address = ctrl->channel0[i];
+ struct dimm_size page_size;
+ struct dimm_size sdram_width;
-static long spd_set_ram_size(const struct mem_controller *ctrl, long dimm_mask)
-{
- int i;
- uint32_t memsz=0;
- uint16_t word;
-
- for(i = 0; i < DIMM_SOCKETS; i++) {
- struct dimm_size sz;
- if (!(dimm_mask & (1 << i))) {
- continue;
- }
- sz = spd_get_dimm_size(ctrl->channel0[i]);
-#if DEBUG_RAM_CONFIG
- print_debug("dimm size =");
- print_debug_hex32(sz.side1);
- print_debug(" ");
- print_debug_hex32(sz.side2);
- print_debug("\r\n");
-#endif
+ if (!(dimm_mask & (1 << i)))
+ continue; // This DIMM not usable
- if (sz.side1 == 0) {
- return -1; /* Report SPD error */
- }
- memsz = set_dimm_size(ctrl, sz, memsz, i);
- }
- /* For now hardset everything at 128MB boundaries */
- /* %ebp has the ram size in multiples of 64MB */
-// cmpl $0, %ebp /* test if there is no mem - smbus went bad */
-// jz no_memory_bad_smbus
- if(memsz < 0x30) {
- /* I should really adjust all of this in C after I have resources
- * to all of the pcie devices.
- */
-
- /* Round up to 128M granularity */
- memsz++;
- memsz &= 0xfe;
- memsz<<= 10;
- word = memsz;
- pci_write_config16(ctrl->d0, 0xc4, word);
- } else {
-
- /* FIXME will this work with 3.5G of ram? */
- /* Put TOLM at 3G */
- pci_write_config16(ctrl->d0, 0xc4, 0xc000);
- /* Hard code a 1G remap window, right after the ram */
- if(memsz< 0x40){
- word = 0x40; /* Ensure we are over 4G */
- } else {
- word = memsz;
+ // Get the relevant parameters via SPD
+ page_size = sdram_spd_get_page_size(dimm_socket_address);
+ sdram_width = sdram_spd_get_width(dimm_socket_address);
+
+ // Update the DRAM Row Attributes.
+ // Page size is encoded as log2(page size in bits) - log2(8 Kb)
+ // NOTE: 8 Kb = 2^13
+ row_attributes |= (page_size.side1 - 13) << (i << 3); // Side 1 of each DIMM is an EVEN row
+
+ if (sdram_width.side2 > 0)
+ row_attributes |= (page_size.side2 - 13) << ((i << 3) + 4); // Side 2 is ODD
+
+ // Set x4 flags if appropriate
+ if (sdram_width.side1 == 4) {
+ row_attributes |= 0x08 << (i << 3);
}
- pci_write_config16(ctrl->d0, 0xc6, word);
- word += 0x10;
- pci_write_config16(ctrl->d0, 0xc8, word);
- }
+ if (sdram_width.side2 == 4) {
+ row_attributes |= 0x08 << ((i << 3) + 4);
+ }
- return dimm_mask;
-}
-
-static void sdram_set_spd_registers(const struct mem_controller *ctrl) {
- long dimm_mask;
-#if DEBUG_RAM_CONFIG
- print_debug(spd_pre_init);
-#endif
- //activate_spd_rom(ctrl);
- dimm_mask = spd_detect_dimms(ctrl);
- if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
- print_debug("No memory for this controller\n");
- return;
- }
- dimm_mask = spd_enable_clocks(ctrl, dimm_mask);
- if (dimm_mask < 0)
- goto hw_spd_err;
- //spd_verify_dimms(ctrl);
-#if DEBUG_RAM_CONFIG
- print_debug(spd_pre_set);
-#endif
- dimm_mask = spd_set_row_attributes(ctrl,dimm_mask);
- if (dimm_mask < 0)
- goto hw_spd_err;
- dimm_mask = spd_set_dram_controller_mode(ctrl,dimm_mask);
- if (dimm_mask < 0)
- goto hw_spd_err;
- dimm_mask = spd_set_cas_latency(ctrl,dimm_mask);
- if (dimm_mask < 0)
- goto hw_spd_err;
- dimm_mask = spd_set_dram_timing(ctrl,dimm_mask);
- if (dimm_mask < 0)
- goto hw_spd_err;
-#if DEBUG_RAM_CONFIG
- print_debug(spd_post_init);
-#endif
- //moved from dram_post_init
- spd_set_ram_size(ctrl, dimm_mask);
- return;
- hw_spd_err:
- /* Unrecoverable error reading SPD data */
- print_err("SPD error - reset\r\n");
- hard_reset();
- return;
+ /* go to the next DIMM */
+ }
+
+ /* Write the new row attributes register */
+ pci_write_config32(PCI_DEV(0, 0, 0), DRA, row_attributes);
}
+//----------------------------------------------------------------------------------
+// Function: enable_e7501_clocks
+// Parameters: dimm_mask - bitmask of populated DIMMs on the board - see
+// spd_get_supported_dimms()
+// Return Value: None
+// Description: Enable clock signals for populated DIMM sockets and disable them
+// for unpopulated sockets (to reduce EMI).
+//
+static void enable_e7501_clocks(uint8_t dimm_mask)
+{
+ int i;
+ uint8_t clock_disable = pci_read_config8(PCI_DEV(0, 0, 0), CKDIS);
- /* I have finally seen ram bad enough to cause LinuxBIOS
- * to die in mysterious ways, before booting up far
- * enough to run a memory tester. This code attempts
- * to catch this blatantly bad ram, with a spot check.
- * For most cases you should boot all of the way up
- * and run a memory tester.
- */
- /* Ensure I read/write each stick of bank of memory &&
- * that I do more than 1000 bytes to avoid the northbridge cache.
- * Only 64M of each side of each DIMM is currently mapped,
- * so we can handle > 4GB of ram here.
- */
-#if 0
-#define bank_msg "Bank "
-#define side_msg " Side "
-static void verify_ram() {
- xorl %ecx, %ecx
- /* Check to see if the RAM is present,
- * in the specified bank and side.
- */
-1: movl %ecx, %ebx
- shrl $1, %ebx
- addl $((5<<8) | SMBUS_MEM_DEVICE_START), %ebx
- CALLSP(smbus_read_byte)
- jz 5f
- testl $1, %ecx
- jz 2f
- cmpb $2, %al
- jne 5f
-
- /* Display the bank and side we are spot checking.
- */
-2: CONSOLE_INFO_TX_STRING($bank_msg)
- movl %ecx, %ebx
- shrl $1, %ebx
- incl %ebx
- CONSOLE_INFO_TX_HEX8(%bl)
- CONSOLE_INFO_TX_STRING($side_msg)
- movl %ecx, %ebx
- andl $1, %ebx
- CONSOLE_INFO_TX_HEX8(%bl)
-
- /* Compute the memory address to spot check. */
- movl %ecx, %ebx
- xorl %eax, %eax
-3: testl %ebx, %ebx
- jz 4f
- addl $0x04000000, %eax
- decl %ebx
- jmp 3b
-4:
- /* Spot check 512K of RAM */
- movl %eax, %ebx
- addl $0x0007ffff, %ebx
- CALLSP(spot_check)
-5:
- /* Now find the next bank and side to spot check */
- incl %ecx
- cmpl $((SMBUS_MEM_DEVICE_END - SMBUS_MEM_DEVICE_START)<<1), %ecx
- jb 1b
- RET_LABEL(verify_ram)
+ for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
+
+ uint8_t socket_mask = 1 << i;
+
+ if (dimm_mask & socket_mask)
+ clock_disable &= ~socket_mask; // DIMM present, enable clock
+ else
+ clock_disable |= socket_mask; // DIMM absent, disable clock
+ }
+ pci_write_config8(PCI_DEV(0, 0, 0), CKDIS, clock_disable);
}
-#endif
-#if 0
-static void ram_postinit(const struct mem_controller *ctrl) {
-#if DEBUG_RAM_CONFIG
- dumpnorth();
-#endif
- /* Include a test to verify that memory is more or less working o.k.
- * This test is to catch programming errors and hardware that is out of
- * spec, not a test to see if the memory dimms are working 100%
- */
-//# CALL_LABEL(verify_ram)
- spd_set_ram_size(ctrl);
+/*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
+/* DIMM-DEDEPENDENT CONFIGURATION FUNCTIONS */
+/**********************************************************************************/
+
+//----------------------------------------------------------------------------------
+// Function: RAM_RESET_DDR_PTR
+// Parameters: ctrl - PCI addresses of memory controller functions, and
+// SMBus addresses of DIMM slots on the mainboard
+// Return Value: None
+// Description: DDR Receive FIFO RE-Sync (?)
+//
+static void RAM_RESET_DDR_PTR(void)
+{
+ uint8_t byte;
+ byte = pci_read_config8(PCI_DEV(0, 0, 0), 0x88);
+ byte |= (1 << 4);
+ pci_write_config8(PCI_DEV(0, 0, 0), 0x88, byte);
+
+ byte = pci_read_config8(PCI_DEV(0, 0, 0), 0x88);
+ byte &= ~(1 << 4);
+ pci_write_config8(PCI_DEV(0, 0, 0), 0x88, byte);
}
-#define FIRST_NORMAL_REFERENCE() CALL_LABEL(ram_postinit)
-#define SPECIAL_FINISHUP() CALL_LABEL(dram_finish)
+//----------------------------------------------------------------------------------
+// Function: ram_set_d0f0_regs
+// Parameters: None
+// Return Value: None
+// Description: Set E7501 registers that are either independent of DIMM specifics,
+// or establish default settings that will be overridden when we
+// learn the specifics.
+// This sets PCI configuration registers to known good values based
+// on the table 'constant_register_values', which are a triple of
+// configuration register offset, mask, and bits to set.
+//
+static void ram_set_d0f0_regs(void)
+{
+ int i;
+ int num_values = ARRAY_SIZE(constant_register_values);
-#endif
+ ASSERT((num_values % 3) == 0); // Bad table?
+
+ for (i = 0; i < num_values; i += 3) {
+
+ uint32_t register_offset = constant_register_values[i];
+ uint32_t bits_to_mask = constant_register_values[i + 1];
+ uint32_t bits_to_set = constant_register_values[i + 2];
+ uint32_t register_value;
-#define ecc_pre_init "Initializing ECC state...\r\n"
-#define ecc_post_init "ECC state initialized.\r\n"
-static void dram_finish(const struct mem_controller *ctrl)
+ // It's theoretically possible to set values for something other than D0:F0,
+ // but it's not typically done here
+ ASSERT(!(register_offset & 0xFFFFFF00));
+
+ // bits_to_mask and bits_to_set should not reference the same bits
+ // Again, not strictly an error, but flagged as a potential bug
+ ASSERT((bits_to_mask & bits_to_set) == 0);
+
+ register_value =
+ pci_read_config32(PCI_DEV(0, 0, 0), register_offset);
+ register_value &= bits_to_mask;
+ register_value |= bits_to_set;
+
+ pci_write_config32(PCI_DEV(0, 0, 0), register_offset,
+ register_value);
+ }
+}
+
+//----------------------------------------------------------------------------------
+// Function: write_8dwords
+// Parameters: src_addr
+// dst_addr
+// Return Value: None
+// Description: Copy 64 bytes from one location to another.
+//
+static void write_8dwords(const uint32_t * src_addr, uint32_t dst_addr)
+{
+ int i;
+ for (i = 0; i < 8; i++) {
+ write32(dst_addr, *src_addr);
+ src_addr++;
+ dst_addr += sizeof(uint32_t);
+ }
+}
+
+//----------------------------------------------------------------------------------
+// Function: ram_set_rcomp_regs
+// Parameters: None
+// Return Value: None
+// Description: Set the E7501's (undocumented) RCOMP registers.
+// Per the 855PM datasheet and IXP2800 HW Initialization Reference
+// Manual, RCOMP registers appear to affect drive strength,
+// pullup/pulldown offset, and slew rate of various signal groups.
+// Comments below are conjecture based on apparent similarity
+// between the E7501 and these two chips.
+//
+static void ram_set_rcomp_regs(void)
{
uint32_t dword;
- uint8_t byte;
- /* Test to see if ECC support is enabled */
- dword = pci_read_config32(ctrl->d0, 0x7c);
- dword >>=20;
- dword &=3;
- if(dword == 2) {
-
-#if DEBUG_RAM_CONFIG
- print_debug(ecc_pre_init);
-#endif
- /* Initialize ECC bits , use ECC zero mode (new to 7501)*/
- pci_write_config8(ctrl->d0, 0x52, 0x06);
- pci_write_config8(ctrl->d0, 0x52, 0x07);
- do {
- byte = pci_read_config8(ctrl->d0, 0x52);
+ uint8_t maybe_strength_control;
- } while ( (byte & 0x08 ) == 0);
+ RAM_DEBUG_MESSAGE("Setting RCOMP registers.\n");
- pci_write_config8(ctrl->d0, 0x52, byte & 0xfc);
-#if DEBUG_RAM_CONFIG
- print_debug(ecc_post_init);
-#endif
+ /*enable access to the rcomp bar */
+ dword = pci_read_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST);
+ dword |= (1 << 22);
+ pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST, dword);
- /* Clear the ECC error bits */
- pci_write_config8(ctrl->d0f1, 0x80, 0x03); /* dev 0, function 1, offset 80 */
- pci_write_config8(ctrl->d0f1, 0x82, 0x03); /* dev 0, function 1, offset 82 */
+ // Set the RCOMP MMIO base address
+ pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_SMRBASE, RCOMP_MMIO);
- pci_write_config32(ctrl->d0f1, 0x40, 1<<18); /* clear dev 0, function 1, offset 40; bit 18 by writing a 1 to it */
- pci_write_config32(ctrl->d0f1, 0x44, 1<<18); /* clear dev 0, function 1, offset 44; bit 18 by writing a 1 to it */
+ // Block RCOMP updates while we configure the registers
+ dword = read32(RCOMP_MMIO + MAYBE_SMRCTL);
+ dword |= (1 << 9);
+ write32(RCOMP_MMIO + MAYBE_SMRCTL, dword);
- pci_write_config8(ctrl->d0, 0x52, 0x0d);
- }
-
- dword = pci_read_config32(ctrl->d0, 0x7c); /* FCS_EN */
- dword |= (1<<17);
- pci_write_config32(ctrl->d0, 0x7c, dword);
+ /* Begin to write the RCOMP registers */
+ // Set CMD and DQ/DQS strength to 2x (?)
+ maybe_strength_control = read8(RCOMP_MMIO + MAYBE_DQCMDSTR) & 0x88;
+ maybe_strength_control |= 0x44;
+ write8(RCOMP_MMIO + MAYBE_DQCMDSTR, maybe_strength_control);
-#if DEBUG_RAM_CONFIG
- dumpnorth();
-#endif
+ write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0x80);
+ write16(RCOMP_MMIO + 0x42, 0);
-// verify_ram();
-}
-#if 0
-#define ERRFUNC(x, str) mem_err(x, str)
-
-
-ERRFUNC(invalid_dimm_type, "Invalid dimm type")
-ERRFUNC(spd_missing_data, "Missing sdram spd data")
-ERRFUNC(spd_invalid_data, "Invalid sdram spd data")
-ERRFUNC(spd_unsupported_data, "Unsupported sdram spd value")
-ERRFUNC(unsupported_page_size, "Unsupported page size")
-ERRFUNC(sdram_presence_mismatch, "DIMM presence mismatch")
-ERRFUNC(sdram_value_mismatch, "spd data does not match")
-ERRFUNC(unsupported_refresh_rate, "Unsuported spd refresh rate")
-ERRFUNC(inconsistent_cas_latencies, "No cas latency supported by all dimms")
-ERRFUNC(unsupported_rcd, "Unsupported ras to cas delay")
-#undef ERRFUNC
-
-#define mem_err_err "ERROR: "
-#define mem_err_pair " on dimm pair "
-#define mem_err_byte " spd byte "
-static void mem_err {
- movl %ebx, %edi
- CONSOLE_ERR_TX_STRING($mem_err_err)
- CONSOLE_ERR_TX_STRING(%esi)
- CONSOLE_ERR_TX_STRING($mem_err_pair)
- movl %edi, %ebx
- subb $(SMBUS_MEM_DEVICE_START), %bl
- CONSOLE_ERR_TX_HEX8(%bl)
- CONSOLE_ERR_TX_STRING($mem_err_byte)
- movl %edi, %ebx
- CONSOLE_ERR_TX_HEX8(%bh)
- jmp mem_stop
+ write_8dwords(maybe_1x_slew_table, RCOMP_MMIO + 0x60);
-}
+ // NOTE: some factory BIOS set 0x9088 here. Seems to work either way.
+ write16(RCOMP_MMIO + 0x40, 0);
-#endif
+ // Set RCVEnOut# strength to 2x (?)
+ maybe_strength_control = read8(RCOMP_MMIO + MAYBE_RCVENSTR) & 0xF8;
+ maybe_strength_control |= 4;
+ write8(RCOMP_MMIO + MAYBE_RCVENSTR, maybe_strength_control);
+ write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0x1c0);
+ write16(RCOMP_MMIO + 0x50, 0);
-#if ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG
-#define ram_enable_1 "Ram Enable 1\r\n"
-#define ram_enable_2 "Ram Enable 2\r\n"
-#define ram_enable_3 "Ram Enable 3\r\n"
-#define ram_enable_4 "Ram Enable 4\r\n"
-#define ram_enable_5 "Ram Enable 5\r\n"
-#define ram_enable_6 "Ram Enable 6\r\n"
-#define ram_enable_7 "Ram Enable 7\r\n"
-#define ram_enable_8 "Ram Enable 8\r\n"
-#define ram_enable_9 "Ram Enable 9\r\n"
-#define ram_enable_10 "Ram Enable 10\r\n"
-#define ram_enable_11 "Ram Enable 11\r\n"
-#endif
+ // Set CS# strength for x4 SDRAM to 2x (?)
+ maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CSBSTR) & 0xF8;
+ maybe_strength_control |= 4;
+ write8(RCOMP_MMIO + MAYBE_CSBSTR, maybe_strength_control);
- /* Estimate that SLOW_DOWN_IO takes about 50&76us*/
- /* delay for 200us */
+ write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0x140);
+ write16(RCOMP_MMIO + 0x48, 0);
-#if 1
-static void do_delay(void)
-{
- int i;
- for(i = 0; i < 16; i++) { SLOW_DOWN_IO }
-}
-#define DO_DELAY do_delay();
-#else
-#define DO_DELAY \
- udelay(200);
-#endif
+ // Set CKE strength for x4 SDRAM to 2x (?)
+ maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CKESTR) & 0xF8;
+ maybe_strength_control |= 4;
+ write8(RCOMP_MMIO + MAYBE_CKESTR, maybe_strength_control);
-#define EXTRA_DELAY DO_DELAY
+ write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0xa0);
+ write16(RCOMP_MMIO + 0x44, 0);
+
+ // Set CK strength for x4 SDRAM to 1x (?)
+ maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CKSTR) & 0xF8;
+ maybe_strength_control |= 1;
+ write8(RCOMP_MMIO + MAYBE_CKSTR, maybe_strength_control);
+
+ write_8dwords(maybe_pull_updown_offset_table, RCOMP_MMIO + 0x180);
+ write16(RCOMP_MMIO + 0x4c, 0);
-static void sdram_enable(int controllers, const struct mem_controller *ctrl)
+ write8(RCOMP_MMIO + 0x2c, 0xff);
+
+ // Set the digital filter length to 8 (?)
+ dword = read32(RCOMP_MMIO + MAYBE_SMRCTL);
+
+ // NOTE: Some factory BIOS don't do this.
+ // Doesn't seem to matter either way.
+ dword &= ~2;
+
+ dword |= 1;
+ write32(RCOMP_MMIO + MAYBE_SMRCTL, dword);
+
+ /* Wait 40 usec */
+ SLOW_DOWN_IO;
+
+ /* unblock updates */
+ dword = read32(RCOMP_MMIO + MAYBE_SMRCTL);
+ dword &= ~(1 << 9);
+ write32(RCOMP_MMIO + MAYBE_SMRCTL, dword);
+
+ // Force a RCOMP measurement cycle?
+ dword |= (1 << 8);
+ write32(RCOMP_MMIO + MAYBE_SMRCTL, dword);
+ dword &= ~(1 << 8);
+ write32(RCOMP_MMIO + MAYBE_SMRCTL, dword);
+
+ /* Wait 40 usec */
+ SLOW_DOWN_IO;
+
+ /*disable access to the rcomp bar */
+ dword = pci_read_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST);
+ dword &= ~(1 << 22);
+ pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST, dword);
+
+}
+
+/*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
+/* DIMM-INDEPENDENT CONFIGURATION FUNCTIONS */
+/**********************************************************************************/
+
+//----------------------------------------------------------------------------------
+// Function: sdram_enable
+// Parameters: controllers - not used
+// ctrl - PCI addresses of memory controller functions, and
+// SMBus addresses of DIMM slots on the mainboard
+// Return Value: None
+// Description: Go through the JEDEC initialization sequence for all DIMMs,
+// then enable refresh and initialize ECC and memory to zero.
+// Upon exit, SDRAM is up and running.
+//
+static void sdram_enable(int controllers,
+ const struct mem_controller *ctrl)
{
- int i;
+ uint8_t dimm_mask = pci_read_config16(PCI_DEV(0, 0, 0), SKPD);
+ uint32_t dram_controller_mode;
+
+ if (dimm_mask == 0)
+ return;
+
/* 1 & 2 Power up and start clocks */
-#if DEBUG_RAM_CONFIG
- print_debug(ram_enable_1);
- print_debug(ram_enable_2);
-#endif
+ RAM_DEBUG_MESSAGE("Ram Enable 1\n");
+ RAM_DEBUG_MESSAGE("Ram Enable 2\n");
/* A 200us delay is needed */
-
- DO_DELAY
- EXTRA_DELAY
+ DO_DELAY; EXTRA_DELAY;
/* 3. Apply NOP */
-#if DEBUG_RAM_CONFIG
- print_debug(ram_enable_3);
-#endif
- RAM_NOP(ctrl);
- EXTRA_DELAY
+ RAM_DEBUG_MESSAGE("Ram Enable 3\n");
+ do_ram_command(RAM_COMMAND_NOP, 0);
+ EXTRA_DELAY;
/* 4 Precharge all */
-#if DEBUG_RAM_CONFIG
- print_debug(ram_enable_4);
-#endif
- RAM_PRECHARGE(ctrl);
- EXTRA_DELAY
-
+ RAM_DEBUG_MESSAGE("Ram Enable 4\n");
+ do_ram_command(RAM_COMMAND_PRECHARGE, 0);
+ EXTRA_DELAY;
/* wait until the all banks idle state... */
+
/* 5. Issue EMRS to enable DLL */
-#if DEBUG_RAM_CONFIG
- print_debug(ram_enable_5);
-#endif
- RAM_EMRS(ctrl);
- EXTRA_DELAY
-
- /* 6. Reset DLL */
-#if DEBUG_RAM_CONFIG
- print_debug(ram_enable_6);
-#endif
- RAM_MRS(ctrl,1);
- EXTRA_DELAY
+ RAM_DEBUG_MESSAGE("Ram Enable 5\n");
+ do_ram_command(RAM_COMMAND_EMRS,
+ SDRAM_EXTMODE_DLL_ENABLE |
+ SDRAM_EXTMODE_DRIVE_NORMAL);
+ EXTRA_DELAY;
+ /* 6. Reset DLL */
+ RAM_DEBUG_MESSAGE("Ram Enable 6\n");
+ set_ram_mode(E7501_SDRAM_MODE | SDRAM_MODE_DLL_RESET);
+ EXTRA_DELAY;
/* Ensure a 200us delay between the DLL reset in step 6 and the final
* mode register set in step 9.
* Infineon needs this before any other command is sent to the ram.
*/
- DO_DELAY
- EXTRA_DELAY
-
+ DO_DELAY; EXTRA_DELAY;
+
/* 7 Precharge all */
-#if DEBUG_RAM_CONFIG
- print_debug(ram_enable_7);
-#endif
- RAM_PRECHARGE(ctrl);
- EXTRA_DELAY
-
+ RAM_DEBUG_MESSAGE("Ram Enable 7\n");
+ do_ram_command(RAM_COMMAND_PRECHARGE, 0);
+ EXTRA_DELAY;
+
/* 8 Now we need 2 AUTO REFRESH / CBR cycles to be performed */
-#if DEBUG_RAM_CONFIG
- print_debug(ram_enable_8);
-#endif
- RAM_CBR(ctrl);
- EXTRA_DELAY
- RAM_CBR(ctrl);
- EXTRA_DELAY
+ RAM_DEBUG_MESSAGE("Ram Enable 8\n");
+ do_ram_command(RAM_COMMAND_CBR, 0);
+ EXTRA_DELAY;
+ do_ram_command(RAM_COMMAND_CBR, 0);
+ EXTRA_DELAY;
+
/* And for good luck 6 more CBRs */
- RAM_CBR(ctrl);
- EXTRA_DELAY
- RAM_CBR(ctrl);
- EXTRA_DELAY
- RAM_CBR(ctrl);
- EXTRA_DELAY
- RAM_CBR(ctrl);
- EXTRA_DELAY
- RAM_CBR(ctrl);
- EXTRA_DELAY
- RAM_CBR(ctrl);
- EXTRA_DELAY
+ do_ram_command(RAM_COMMAND_CBR, 0);
+ EXTRA_DELAY;
+ do_ram_command(RAM_COMMAND_CBR, 0);
+ EXTRA_DELAY;
+ do_ram_command(RAM_COMMAND_CBR, 0);
+ EXTRA_DELAY;
+ do_ram_command(RAM_COMMAND_CBR, 0);
+ EXTRA_DELAY;
+ do_ram_command(RAM_COMMAND_CBR, 0);
+ EXTRA_DELAY;
+ do_ram_command(RAM_COMMAND_CBR, 0);
+ EXTRA_DELAY;
/* 9 mode register set */
-#if DEBUG_RAM_CONFIG
- print_debug(ram_enable_9);
-#endif
- RAM_MRS(ctrl,0);
- EXTRA_DELAY
-
+ RAM_DEBUG_MESSAGE("Ram Enable 9\n");
+ set_ram_mode(E7501_SDRAM_MODE | SDRAM_MODE_NORMAL);
+ EXTRA_DELAY;
+
/* 10 DDR Receive FIFO RE-Sync */
-#if DEBUG_RAM_CONFIG
- print_debug(ram_enable_10);
-#endif
- RAM_RESET_DDR_PTR(ctrl);
- EXTRA_DELAY
-
+ RAM_DEBUG_MESSAGE("Ram Enable 10\n");
+ RAM_RESET_DDR_PTR();
+ EXTRA_DELAY;
+
/* 11 normal operation */
-#if DEBUG_RAM_CONFIG
- print_debug(ram_enable_11);
-#endif
- RAM_NORMAL(ctrl);
+ RAM_DEBUG_MESSAGE("Ram Enable 11\n");
+ do_ram_command(RAM_COMMAND_NORMAL, 0);
+ EXTRA_DELAY;
+
+ // Reconfigure the row boundaries and Top of Low Memory
+ // to match the true size of the DIMMs
+ configure_e7501_ram_addresses(ctrl, dimm_mask);
+
+ /* Finally enable refresh */
+ dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC);
+ dram_controller_mode |= (1 << 29);
+ pci_write_config32(PCI_DEV(0, 0, 0), DRC, dram_controller_mode);
+ EXTRA_DELAY;
+ initialize_ecc();
+
+ dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC); /* FCS_EN */
+ dram_controller_mode |= (1 << 17); // NOTE: undocumented reserved bit
+ pci_write_config32(PCI_DEV(0, 0, 0), DRC, dram_controller_mode);
+
+ RAM_DEBUG_MESSAGE("Northbridge following SDRAM init:\n");
+ DUMPNORTH();
+}
+
+//----------------------------------------------------------------------------------
+// Function: sdram_set_spd_registers
+// Parameters: ctrl - PCI addresses of memory controller functions, and
+// SMBus addresses of DIMM slots on the mainboard
+// Return Value: None
+// Description: Configure SDRAM controller parameters that depend on
+// characteristics of the DIMMs installed in the system. These
+// characteristics are read from the DIMMs via the standard Serial
+// Presence Detect (SPD) interface.
+//
+static void sdram_set_spd_registers(const struct mem_controller *ctrl)
+{
+ uint8_t dimm_mask;
+
+ RAM_DEBUG_MESSAGE("Reading SPD data...\n");
+
+ dimm_mask = spd_get_supported_dimms(ctrl);
+ if (dimm_mask == 0) {
+ print_debug("No usable memory for this controller\n");
+ } else {
+ enable_e7501_clocks(dimm_mask);
- // special from v1
- //FIRST_NORMAL_REFERENCE();
- //spd_set_ram_size(ctrl, 0x03);
+ RAM_DEBUG_MESSAGE("setting based on SPD data...\n");
- /* Finally enable refresh */
- ENABLE_REFRESH(ctrl);
+ configure_e7501_row_attributes(ctrl, dimm_mask);
+ configure_e7501_dram_controller_mode(ctrl, dimm_mask);
+ configure_e7501_cas_latency(ctrl, dimm_mask);
+ RAM_RESET_DDR_PTR();
- //SPECIAL_FINISHUP();
- dram_finish(ctrl);
+ configure_e7501_dram_timing(ctrl, dimm_mask);
+ DO_DELAY;
+ RAM_DEBUG_MESSAGE("done\n");
+ }
+
+ /* NOTE: configure_e7501_ram_addresses() is NOT called here.
+ * We want to keep the default 64 MB/row mapping until sdram_enable() is called,
+ * even though the default mapping is almost certainly incorrect.
+ * The default mapping makes it easy to initialize all of the DIMMs
+ * even if the total system memory is > 4 GB.
+ *
+ * Save the dimm_mask for when sdram_enable is called, so it can call
+ * configure_e7501_ram_addresses() without having to regenerate the bitmask
+ * of usable DIMMs.
+ */
+ pci_write_config16(PCI_DEV(0, 0, 0), SKPD, dimm_mask);
+}
+
+//----------------------------------------------------------------------------------
+// Function: sdram_set_registers
+// Parameters: ctrl - PCI addresses of memory controller functions, and
+// SMBus addresses of DIMM slots on the mainboard
+// Return Value: None
+// Description: Do basic ram setup that does NOT depend on serial presence detect
+// information (i.e. independent of DIMM specifics).
+//
+static void sdram_set_registers(const struct mem_controller *ctrl)
+{
+ RAM_DEBUG_MESSAGE("Northbridge prior to SDRAM init:\n");
+ DUMPNORTH();
+ ram_set_rcomp_regs();
+ ram_set_d0f0_regs();
}
+/*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
+/* PUBLIC INTERFACE */
+/**********************************************************************************/
projects / coreboot.git / blobdiff