#include <spd.h>
#include "southbridge/amd/cs5536/cs5536.h"
-static const unsigned char NumColAddr[] = {
- 0x00, 0x10, 0x11, 0x00, 0x00, 0x00, 0x00, 0x07,
- 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F
+static const unsigned char NumColAddr[] = {
+ 0x00, 0x10, 0x11, 0x00, 0x00, 0x00, 0x00, 0x07,
+ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F
};
-void banner(char *s)
+static void banner(const char *s)
{
- print_debug("===========================");
- print_debug(s);
- print_debug("======================================\r\n");
+ printk(BIOS_DEBUG, " * %s\n", s);
}
-void hcf(void)
+
+static void hcf(void)
{
- print_emerg("DIE\r\n");
- /* this guarantees we flush the UART fifos (if any) and also
- * ensures that things, in general, keep going so no debug output
+ print_emerg("DIE\n");
+ /* this guarantees we flush the UART fifos (if any) and also
+ * ensures that things, in general, keep going so no debug output
* is lost
*/
while (1)
spd_byte = spd_read_byte(dimm, SPD_NUM_DIMM_BANKS);
if ((MIN_MOD_BANKS > spd_byte) || (spd_byte > MAX_MOD_BANKS)) {
print_emerg("Number of module banks not compatible\n");
- POST_CODE(ERROR_BANK_SET);
+ post_code(ERROR_BANK_SET);
hcf();
}
dimm_setting |= (spd_byte >> 1) << CF07_UPPER_D0_MB_SHIFT;
spd_byte = spd_read_byte(dimm, SPD_NUM_BANKS_PER_SDRAM);
if ((MIN_DEV_BANKS > spd_byte) || (spd_byte > MAX_DEV_BANKS)) {
print_emerg("Number of device banks not compatible\n");
- POST_CODE(ERROR_BANK_SET);
+ post_code(ERROR_BANK_SET);
hcf();
}
dimm_setting |= (spd_byte >> 2) << CF07_UPPER_D0_CB_SHIFT;
if ((spd_read_byte(dimm, SPD_NUM_ROWS) & 0xF0)
|| (spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF0)) {
print_emerg("Assymetirc DIMM not compatible\n");
- POST_CODE(ERROR_UNSUPPORTED_DIMM);
+ post_code(ERROR_UNSUPPORTED_DIMM);
hcf();
}
banner("SPDBANKDENSITY");
banner("TEST DIMM SIZE>8");
if (dimm_size > 8) { /* 8 is 1GB only support 1GB per DIMM */
print_emerg("Only support up to 1 GB per DIMM\n");
- POST_CODE(ERROR_DENSITY_DIMM);
+ post_code(ERROR_DENSITY_DIMM);
hcf();
}
dimm_setting |= dimm_size << CF07_UPPER_D0_SZ_SHIFT;
banner("MAXCOLADDR");
if (spd_byte > MAX_COL_ADDR) {
print_emerg("DIMM page size not compatible\n");
- POST_CODE(ERROR_SET_PAGE);
+ post_code(ERROR_SET_PAGE);
hcf();
}
banner(">12address test");
/* I don't think you need this check.
if (spd_byte0 >= 0xA0 || spd_byte1 >= 0xA0){
print_emerg("DIMM overclocked. Check GeodeLink Speed\n");
- POST_CODE(POST_PLL_MEM_FAIL);
+ post_code(POST_PLL_MEM_FAIL);
hcf();
} */
/* current speed > max speed? */
if (GeodeLinkSpeed() > speed) {
- print_emerg("DIMM overclocked. Check GeodeLink Speed\r\n");
- POST_CODE(POST_PLL_MEM_FAIL);
+ print_emerg("DIMM overclocked. Check GeodeLink Speed\n");
+ post_code(POST_PLL_MEM_FAIL);
hcf();
}
}
}
msr = rdmsr(MC_CF07_DATA);
- msr.lo |= ((rate0 * (GeodeLinkSpeed() / 2)) / 16)
+ msr.lo |= ((rate0 * (GeodeLinkSpeed() / 2)) / 16)
<< CF07_LOWER_REF_INT_SHIFT;
wrmsr(MC_CF07_DATA, msr);
}
const uint8_t CASDDR[] = { 5, 5, 2, 6, 3, 7, 4, 0 }; /* 1(1.5), 1.5, 2, 2.5, 3, 3.5, 4, 0 */
-static void setCAS(void)
+static u8 getcasmap(u32 dimm, u16 glspeed)
{
-/*;*****************************************************************************
-;*
-;* setCAS
-;* EEPROM byte usage: (18) SDRAM device attributes - CAS latency
-;* EEPROM byte usage: (23) SDRAM Minimum Clock Cycle Time @ CLX -.5
-;* EEPROM byte usage: (25) SDRAM Minimum Clock Cycle Time @ CLX -1
-;*
-;* The CAS setting is based on the information provided in each DIMMs SPD.
-;* The speed at which a DIMM can run is described relative to the slowest
-;* CAS the DIMM supports. Each speed for the relative CAS settings is
-;* checked that it is within the GeodeLink speed. If it isn't within the GeodeLink
-;* speed, the CAS setting is removed from the list of good settings for
-;* the DIMM. This is done for both DIMMs and the lists are compared to
-;* find the lowest common CAS latency setting. If there are no CAS settings
-;* in common we out a ERROR_DIFF_DIMMS (78h) to port 80h and halt.
-;*
-;* Entry:
-;* Exit: Set fastest CAS Latency based on GeodeLink speed and SPD information.
-;* Destroys: We really use everything !
-;*****************************************************************************/
- uint16_t glspeed, dimm_speed;
- uint8_t spd_byte, casmap0, casmap1, casmap_shift;
- msr_t msr;
-
- glspeed = GeodeLinkSpeed();
+ u16 dimm_speed;
+ u8 spd_byte, casmap, casmap_shift=0;
/************************** DIMM0 **********************************/
- casmap0 = spd_read_byte(DIMM0, SPD_ACCEPTABLE_CAS_LATENCIES);
- if (casmap0 != 0xFF) {
+ casmap = spd_read_byte(dimm, SPD_ACCEPTABLE_CAS_LATENCIES);
+ if (casmap != 0xFF) {
/* IF -.5 timing is supported, check -.5 timing > GeodeLink */
- spd_byte = spd_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_2ND);
+ spd_byte = spd_read_byte(dimm, SPD_SDRAM_CYCLE_TIME_2ND);
if (spd_byte != 0) {
/* Turn SPD ns time into MHZ. Check what the asm does to this math. */
dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F));
if (dimm_speed >= glspeed) {
casmap_shift = 1; /* -.5 is a shift of 1 */
/* IF -1 timing is supported, check -1 timing > GeodeLink */
- spd_byte = spd_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_3RD);
+ spd_byte = spd_read_byte(dimm, SPD_SDRAM_CYCLE_TIME_3RD);
if (spd_byte != 0) {
/* Turn SPD ns time into MHZ. Check what the asm does to this math. */
dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F));
}
} /* SPD_SDRAM_CYCLE_TIME_2ND (-.5) !=0 */
/* set the casmap based on the shift to limit possible CAS settings */
- spd_byte = 31 - __builtin_clz((uint32_t) casmap0);
+ spd_byte = 31 - __builtin_clz((uint32_t) casmap);
/* just want bits in the lower byte since we have to cast to a 32 */
- casmap0 &= 0xFF << (spd_byte - casmap_shift);
+ casmap &= 0xFF << (spd_byte - casmap_shift);
} else { /* No DIMM */
- casmap0 = 0;
+ casmap = 0;
}
+ return casmap;
+}
- /************************** DIMM1 **********************************/
- casmap1 = spd_read_byte(DIMM1, SPD_ACCEPTABLE_CAS_LATENCIES);
- if (casmap1 != 0xFF) {
- /* IF -.5 timing is supported, check -.5 timing > GeodeLink */
- spd_byte = spd_read_byte(DIMM1, SPD_SDRAM_CYCLE_TIME_2ND);
- if (spd_byte != 0) {
- /* Turn SPD ns time into MHZ. Check what the asm does to this math. */
- dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F));
- if (dimm_speed >= glspeed) {
- casmap_shift = 1; /* -.5 is a shift of 1 */
- /* IF -1 timing is supported, check -1 timing > GeodeLink */
- spd_byte = spd_read_byte(DIMM1, SPD_SDRAM_CYCLE_TIME_3RD);
- if (spd_byte != 0) {
- /* Turn SPD ns time into MHZ. Check what the asm does to this math. */
- dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F));
- if (dimm_speed >= glspeed) {
- casmap_shift = 2; /* -1 is a shift of 2 */
- }
- /* note that the -1 result doesn't need to change the available CAS map */
- } /* SPD_SDRAM_CYCLE_TIME_3RD (-1) !=0 */
- } else {
- casmap_shift = 0;
- }
- } /* SPD_SDRAM_CYCLE_TIME_2ND (-.5) !=0 */
- /* set the casmap based on the shift to limit possible CAS settings */
- spd_byte = 31 - __builtin_clz((uint32_t) casmap1);
- /* just want bits in the lower byte since we have to cast to a 32 */
- casmap1 &= 0xFF << (spd_byte - casmap_shift);
- } else { /* No DIMM */
- casmap1 = 0;
- }
+static void setCAS(void)
+{
+/*;*****************************************************************************
+;*
+;* setCAS
+;* EEPROM byte usage: (18) SDRAM device attributes - CAS latency
+;* EEPROM byte usage: (23) SDRAM Minimum Clock Cycle Time @ CLX -.5
+;* EEPROM byte usage: (25) SDRAM Minimum Clock Cycle Time @ CLX -1
+;*
+;* The CAS setting is based on the information provided in each DIMMs SPD.
+;* The speed at which a DIMM can run is described relative to the slowest
+;* CAS the DIMM supports. Each speed for the relative CAS settings is
+;* checked that it is within the GeodeLink speed. If it isn't within the GeodeLink
+;* speed, the CAS setting is removed from the list of good settings for
+;* the DIMM. This is done for both DIMMs and the lists are compared to
+;* find the lowest common CAS latency setting. If there are no CAS settings
+;* in common we out a ERROR_DIFF_DIMMS (78h) to port 80h and halt.
+;*
+;* Entry:
+;* Exit: Set fastest CAS Latency based on GeodeLink speed and SPD information.
+;* Destroys: We really use everything !
+;*****************************************************************************/
+ uint16_t glspeed;
+ uint8_t spd_byte, casmap0, casmap1;
+ msr_t msr;
+
+ glspeed = GeodeLinkSpeed();
+
+ casmap0 = getcasmap(DIMM0, glspeed);
+ casmap1 = getcasmap(DIMM1, glspeed);
/********************* CAS_LAT MAP COMPARE ***************************/
if (casmap0 == 0) {
- spd_byte = CASDDR[__builtin_ctz((uint32_t) casmap1)];
+ spd_byte = CASDDR[__builtin_ctz(casmap1)];
} else if (casmap1 == 0) {
- spd_byte = CASDDR[__builtin_ctz((uint32_t) casmap0)];
+ spd_byte = CASDDR[__builtin_ctz(casmap0)];
} else if ((casmap0 &= casmap1)) {
- spd_byte = CASDDR[__builtin_ctz((uint32_t) casmap0)];
+ spd_byte = CASDDR[__builtin_ctz(casmap0)];
} else {
- print_emerg("DIMM CAS Latencies not compatible\r\n");
- POST_CODE(ERROR_DIFF_DIMMS);
+ print_emerg("DIMM CAS Latencies not compatible\n");
+ post_code(ERROR_DIFF_DIMMS);
hcf();
}
wrmsr(MC_CF07_DATA, msr);
}
+#undef TLA_MEMORY_DEBUG
+#ifdef TLA_MEMORY_DEBUG
static void EnableMTest(void)
{
msr_t msr;
msr.lo |= CFCLK_LOWER_TRISTATE_DIS_SET;
wrmsr(MC_CFCLK_DBUG, msr);
- print_info("Enabled MTest for TLA debug\r\n");
+ print_info("Enabled MTest for TLA debug\n");
}
+#endif
static void sdram_set_registers(const struct mem_controller *ctrl)
{
{
uint8_t spd_byte;
- banner("sdram_set_spd_register\n");
- POST_CODE(POST_MEM_SETUP); // post_70h
+ banner("sdram_set_spd_register");
+ post_code(POST_MEM_SETUP); // post_70h
spd_byte = spd_read_byte(DIMM0, SPD_MODULE_ATTRIBUTES);
banner("Check DIMM 0");
/* Check DIMM is not Register and not Buffered DIMMs. */
if ((spd_byte != 0xFF) && (spd_byte & 3)) {
- print_emerg("DIMM0 NOT COMPATIBLE\r\n");
- POST_CODE(ERROR_UNSUPPORTED_DIMM);
+ print_emerg("DIMM0 NOT COMPATIBLE\n");
+ post_code(ERROR_UNSUPPORTED_DIMM);
hcf();
}
banner("Check DIMM 1");
spd_byte = spd_read_byte(DIMM1, SPD_MODULE_ATTRIBUTES);
if ((spd_byte != 0xFF) && (spd_byte & 3)) {
print_emerg("DIMM1 NOT COMPATIBLE\n");
- POST_CODE(ERROR_UNSUPPORTED_DIMM);
+ post_code(ERROR_UNSUPPORTED_DIMM);
hcf();
}
- POST_CODE(POST_MEM_SETUP2); // post_72h
+ post_code(POST_MEM_SETUP2); // post_72h
banner("Check DDR MAX");
/* Check that the memory is not overclocked. */
checkDDRMax();
/* Size the DIMMS */
- POST_CODE(POST_MEM_SETUP3); // post_73h
+ post_code(POST_MEM_SETUP3); // post_73h
banner("AUTOSIZE DIMM 0");
auto_size_dimm(DIMM0);
- POST_CODE(POST_MEM_SETUP4); // post_74h
+ post_code(POST_MEM_SETUP4); // post_74h
banner("AUTOSIZE DIMM 1");
auto_size_dimm(DIMM1);
/* Set CAS latency */
banner("set cas latency");
- POST_CODE(POST_MEM_SETUP5); // post_75h
+ post_code(POST_MEM_SETUP5); // post_75h
setCAS();
/* Set all the other latencies here (tRAS, tRP....) */
;* 9) MRS w/ memory config & reset DLL clear
;* 8) DDR SDRAM ready for normal operation
;********************************************************************/
- POST_CODE(POST_MEM_ENABLE); // post_76h
+ post_code(POST_MEM_ENABLE); // post_76h
+#ifdef TLA_MEMORY_DEBUG
/* Only enable MTest for TLA memory debug */
- /*EnableMTest(); */
+ EnableMTest();
+#endif
/* If both Page Size = "Not Installed" we have a problems and should halt. */
msr = rdmsr(MC_CF07_DATA);
- if ((msr.hi & ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) ==
+ if ((msr.hi & ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) ==
((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) {
- print_emerg("No memory in the system\r\n");
- POST_CODE(ERROR_NO_DIMMS);
+ print_emerg("No memory in the system\n");
+ post_code(ERROR_NO_DIMMS);
hcf();
}
msr.lo |= (209 << 8); /* bits[15:8] = 209 */
wrmsr(msrnum, msr);
- print_emerg("DRAM controller init done.\n");
- POST_CODE(POST_MEM_SETUP_GOOD); //0x7E
+ banner("DRAM controller init done.\n");
+ post_code(POST_MEM_SETUP_GOOD); //0x7E
/* make sure there is nothing stale in the cache */
/* CAR stack is in the cache __asm__ __volatile__("wbinvd\n"); */
projects / coreboot.git / blobdiff