-#define POST_CODE(x) outb(0x80, x)
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
-static void pll_reset(void)
+static void pll_reset(char manualconf)
{
msr_t msrGlcpSysRstpll;
- msrGlcpSysRstpll = rdmsr(GLCP_SYS_RSTPLL);
-
- print_debug("MSR GLCP_SYS_RSTPLL (");
- print_debug_hex32(GLCP_SYS_RSTPLL);
- print_debug(") value is: ");
- print_debug_hex32(msrGlcpSysRstpll.hi);
- print_debug(":");
- print_debug_hex32(msrGlcpSysRstpll.lo);
- print_debug("\n");
-
- msrGlcpSysRstpll.lo &= 0x80000000;
+ msrGlcpSysRstpll = rdmsr(GLCP_SYS_RSTPLL);
- // If the "we've already been here" flag is set, don't reconfigure the pll
- if ( !(msrGlcpSysRstpll.lo) )
- { // we haven't configured the PLL; do it now
- POST_CODE(0x77);
-
- /*
- * 64 - 32 | 31-0
- *
- * (03FB)
- * 0000 0011 1111 1011 | 1000 0000 1101 1110 0000 0000 1000 0001
- *
- * (039C)
- * 0000 0011 1001 1100 | 1000 0000 1101 1110 0000 0000 1000 0001
- *
- * (029C)
- * 0000 0010 1001 1100 | 1000 0000 1101 1110 0000 0000 1000 0001
- *
- * (02CB)
- * 0000 0010 1100 1011 | 1000 0000 1101 1110 0000 0000 1000 0001
- *
- * 00101 1 00101 1 | 100000 0 0 11011110 0000 0000 1000 0001
- * GLIUMULT GLIUDIV COREMULT COREDIV | SWFLAGS (RO) (RO) HOLD_COUNT
- */
-
- /* ### 02CB ###
- * GLIUMULT = 6
- * GLIUDIV = 2
- * COREMULT = 6
- * COREDIV = 2
- *
- * ### 03FB ###
- * GLIUMULT = 8
- * GLIUDIV = 2
- * COREMULT = 30
- * COREDIV = 2
- *
- * ### 039C ### bad... why?
- * GLIUMULT = 8
- * GLIUDIV = 0
- * COREMULT = 15
- * COREDIV = 0
- *
- * ### 029C ### good...
- * GLIUMULT = 6
- * GLIUDIV = 0
- * COREMULT = 15
- * COREDIV = 0
- *
- * CLOCK = 33 MHz
- *
- */
+ print_debug("_MSR GLCP_SYS_RSTPLL (");
+ print_debug_hex32(GLCP_SYS_RSTPLL);
+ print_debug(") value is: ");
+ print_debug_hex32(msrGlcpSysRstpll.hi);
+ print_debug(":");
+ print_debug_hex32(msrGlcpSysRstpll.lo);
+ print_debug("\n");
+ POST_CODE(POST_PLL_INIT);
+ if (!(msrGlcpSysRstpll.lo & (1 << RSTPLL_LOWER_SWFLAGS_SHIFT))) {
+ print_debug("Configuring PLL\n");
+ if (manualconf) {
+ POST_CODE(POST_PLL_MANUAL);
/* CPU and GLIU mult/div (GLMC_CLK = GLIU_CLK / 2) */
- msrGlcpSysRstpll.hi = 0x0000029C;
+ msrGlcpSysRstpll.hi = PLLMSRhi;
/* Hold Count - how long we will sit in reset */
- msrGlcpSysRstpll.lo = 0x00DE0000;
+ msrGlcpSysRstpll.lo = PLLMSRlo;
+ } else {
+ /*automatic configuration (straps) */
+ POST_CODE(POST_PLL_STRAP);
+ msrGlcpSysRstpll.lo &=
+ ~(0xFF << RSTPPL_LOWER_HOLD_COUNT_SHIFT);
+ msrGlcpSysRstpll.lo |=
+ (0xDE << RSTPPL_LOWER_HOLD_COUNT_SHIFT);
+ msrGlcpSysRstpll.lo &=
+ ~(RSTPPL_LOWER_COREBYPASS_SET |
+ RSTPPL_LOWER_MBBYPASS_SET);
+ msrGlcpSysRstpll.lo |=
+ RSTPPL_LOWER_COREPD_SET | RSTPPL_LOWER_CLPD_SET;
+ }
+ /* Use SWFLAGS to remember: "we've already been here" */
+ msrGlcpSysRstpll.lo |= (1 << RSTPLL_LOWER_SWFLAGS_SHIFT);
- /* Use SWFLAGS to remember: "we've already been here" */
- msrGlcpSysRstpll.lo |= 0x80000000;
+ /* "reset the chip" value */
+ msrGlcpSysRstpll.lo |= RSTPPL_LOWER_CHIP_RESET_SET;
+ wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
- /* "reset the chip" value */
- msrGlcpSysRstpll.lo |= 0x00000001;
+ /* You should never get here..... The chip has reset. */
+ print_debug("CONFIGURING PLL FAILURE\n");
+ POST_CODE(POST_PLL_RESET_FAIL);
+ __asm__ __volatile__("hlt\n");
- wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
+ }
+ print_debug("Done pll_reset\r\n");
+ return;
+}
+
+static unsigned int CPUSpeed(void)
+{
+ unsigned int speed;
+ msr_t msr;
+
+ msr = rdmsr(GLCP_SYS_RSTPLL);
+ speed = ((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) & 0x1F) + 1) * 333) / 10;
+ if ((((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) & 0x1F) + 1) * 333) % 10) > 5) {
+ ++speed;
+ }
+ return (speed);
+}
+static unsigned int GeodeLinkSpeed(void)
+{
+ unsigned int speed;
+ msr_t msr;
+
+ msr = rdmsr(GLCP_SYS_RSTPLL);
+ speed = ((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & 0x1F) + 1) * 333) / 10;
+ if ((((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & 0x1F) + 1) * 333) % 10) > 5) {
+ ++speed;
+ }
+ return (speed);
+}
+static unsigned int PCISpeed(void)
+{
+ msr_t msr;
+
+ msr = rdmsr(GLCP_SYS_RSTPLL);
+ if (msr.hi & (1 << RSTPPL_LOWER_PCISPEED_SHIFT)) {
+ return (66);
+ } else {
+ return (33);
}
}
projects / coreboot.git / blobdiff