Please bear with me - another rename checkin. This qualifies as trivial, no

[coreboot.git] / src / northbridge / amd / lx / pll_reset.c

diff --git a/src/northbridge/amd/lx/pll_reset.c b/src/northbridge/amd/lx/pll_reset.c
index 4795665e6cbce8b592e8cca08286091c387d3e2a..45a2c9338cdaf495a8ceb00499b078bd39647821 100644 (file)
--- a/src/northbridge/amd/lx/pll_reset.c
+++ b/src/northbridge/amd/lx/pll_reset.c
@@ -1,5 +1,5 @@
 /*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
  *
  * Copyright (C) 2007 Advanced Micro Devices, Inc.
  *
@@ -22,83 +22,88 @@ static void pll_reset(char manualconf)
 {
        msr_t msrGlcpSysRstpll;
 
-        msrGlcpSysRstpll = rdmsr(GLCP_SYS_RSTPLL);
-       
+       msrGlcpSysRstpll = rdmsr(GLCP_SYS_RSTPLL);
+
        print_debug("_MSR GLCP_SYS_RSTPLL (");
-               print_debug_hex32(GLCP_SYS_RSTPLL);
-               print_debug(") value is: ");
-               print_debug_hex32(msrGlcpSysRstpll.hi);
-               print_debug(":");
-               print_debug_hex32(msrGlcpSysRstpll.lo);
-               print_debug("\r\n");
+       print_debug_hex32(GLCP_SYS_RSTPLL);
+       print_debug(") value is: ");
+       print_debug_hex32(msrGlcpSysRstpll.hi);
+       print_debug(":");
+       print_debug_hex32(msrGlcpSysRstpll.lo);
+       print_debug("\n");
        POST_CODE(POST_PLL_INIT);
-       
-       if (!(msrGlcpSysRstpll.lo & (1 << RSTPLL_LOWER_SWFLAGS_SHIFT))){
+
+       if (!(msrGlcpSysRstpll.lo & (1 << RSTPLL_LOWER_SWFLAGS_SHIFT))) {
                print_debug("Configuring PLL\n");
-               if(manualconf){
+               if (manualconf) {
                        POST_CODE(POST_PLL_MANUAL);
                        /* CPU and GLIU mult/div (GLMC_CLK = GLIU_CLK / 2)  */
-               msrGlcpSysRstpll.hi = PLLMSRhi;
+                       msrGlcpSysRstpll.hi = PLLMSRhi;
 
                        /* Hold Count - how long we will sit in reset */
-               msrGlcpSysRstpll.lo = PLLMSRlo;
-               }
-               else{
-                       /*automatic configuration (straps)*/
+                       msrGlcpSysRstpll.lo = PLLMSRlo;
+               } else {
+                       /*automatic configuration (straps) */
                        POST_CODE(POST_PLL_STRAP);
-                       msrGlcpSysRstpll.lo &= ~(0xFF << RSTPPL_LOWER_HOLD_COUNT_SHIFT);
-                       msrGlcpSysRstpll.lo |= (0xDE << RSTPPL_LOWER_HOLD_COUNT_SHIFT);
-                       msrGlcpSysRstpll.lo &= ~(RSTPPL_LOWER_COREBYPASS_SET | RSTPPL_LOWER_MBBYPASS_SET);
-                       msrGlcpSysRstpll.lo |= RSTPPL_LOWER_COREPD_SET | RSTPPL_LOWER_CLPD_SET;
+                       msrGlcpSysRstpll.lo &=
+                           ~(0xFF << RSTPPL_LOWER_HOLD_COUNT_SHIFT);
+                       msrGlcpSysRstpll.lo |=
+                           (0xDE << RSTPPL_LOWER_HOLD_COUNT_SHIFT);
+                       msrGlcpSysRstpll.lo &=
+                           ~(RSTPPL_LOWER_COREBYPASS_SET |
+                             RSTPPL_LOWER_MBBYPASS_SET);
+                       msrGlcpSysRstpll.lo |=
+                           RSTPPL_LOWER_COREPD_SET | RSTPPL_LOWER_CLPD_SET;
                }
-                       /* Use SWFLAGS to remember: "we've already been here"  */
+               /* Use SWFLAGS to remember: "we've already been here"  */
                msrGlcpSysRstpll.lo |= (1 << RSTPLL_LOWER_SWFLAGS_SHIFT);
 
-                       /* "reset the chip" value */
+               /* "reset the chip" value */
                msrGlcpSysRstpll.lo |= RSTPPL_LOWER_CHIP_RESET_SET;
                wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
 
-               /*      You should never get here..... The chip has reset.*/
+               /*      You should never get here..... The chip has reset. */
                print_debug("CONFIGURING PLL FAILURE\n");
                POST_CODE(POST_PLL_RESET_FAIL);
                __asm__ __volatile__("hlt\n");
 
        }
-       print_debug("Done cpuRegInit\n");
+       print_debug("Done pll_reset\r\n");
        return;
 }
 
-static unsigned int CPUSpeed(void){
+static unsigned int CPUSpeed(void)
+{
        unsigned int speed;
        msr_t msr;
 
        msr = rdmsr(GLCP_SYS_RSTPLL);
-       speed = ((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) & 0x1F)+1)*333)/10;
-       if((((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) & 0x1F)+1)*333)%10) > 5){
+       speed = ((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) & 0x1F) + 1) * 333) / 10;
+       if ((((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) & 0x1F) + 1) * 333) % 10) > 5) {
                ++speed;
        }
-       return(speed);
+       return (speed);
 }
-static unsigned int GeodeLinkSpeed(void){
+static unsigned int GeodeLinkSpeed(void)
+{
        unsigned int speed;
        msr_t msr;
 
        msr = rdmsr(GLCP_SYS_RSTPLL);
-       speed = ((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & 0x1F)+1)*333)/10;
-       if((((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & 0x1F)+1)*333)%10) > 5){
+       speed = ((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & 0x1F) + 1) * 333) / 10;
+       if ((((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & 0x1F) + 1) * 333) % 10) > 5) {
                ++speed;
        }
-       return(speed);
+       return (speed);
 }
-static unsigned int PCISpeed(void){
+static unsigned int PCISpeed(void)
+{
        msr_t msr;
 
        msr = rdmsr(GLCP_SYS_RSTPLL);
-       if (msr.hi & (1 << RSTPPL_LOWER_PCISPEED_SHIFT)){
-               return(66);
-       }
-       else{
-               return(33);
+       if (msr.hi & (1 << RSTPPL_LOWER_PCISPEED_SHIFT)) {
+               return (66);
+       } else {
+               return (33);
        }
 }
-