/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
#include <cpu/x86/msr.h>
#include <cpu/x86/cache.h>
#include <cpu/amd/vr.h>
+#include <cpu/cpu.h>
#include "chip.h"
#include "northbridge.h"
+#include "../../../southbridge/amd/cs5536/cs5536.h"
+
/* here is programming for the various MSRs.*/
#define IM_QWAIT 0x100000
#define IOD_BM(msr, pdid1, bizarro, ibase, imask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(ibase>>12), .lo=(ibase<<20)|imask}}
#define IOD_SC(msr, pdid1, bizarro, en, wen, ren, ibase) {msr, {.hi=(pdid1<<29)|(bizarro<<28), .lo=(en<<24)|(wen<<21)|(ren<<20)|(ibase<<3)}}
-#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
-
-extern void graphics_init(void);
-extern void cpubug(void);
-extern void chipsetinit(void);
-extern void print_conf(void);
-extern uint32_t get_systop(void);
-
-void northbridge_init_early(void);
-void setup_realmode_idt(void);
+void print_conf(void);
+void graphics_init(void);
void do_vsmbios(void);
struct msr_defaults {
0}
};
-/* todo: add a resource record. We don't do this here because this may be called when
+/* Print the platform configuration - do before PCI init or it will not
+ * work right.
+ */
+void print_conf(void)
+{
+#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR
+ int i;
+ unsigned long iol;
+ msr_t msr;
+
+ int cpu_msr_defs[] = { CPU_BC_L2_CONF, CPU_IM_CONFIG, CPU_DM_CONFIG0,
+ CPU_RCONF_DEFAULT, CPU_RCONF_BYPASS, CPU_RCONF_A0_BF,
+ CPU_RCONF_C0_DF, CPU_RCONF_E0_FF, CPU_RCONF_SMM, CPU_RCONF_DMM,
+ GLCP_DELAY_CONTROLS, GL_END
+ };
+
+ int gliu0_msr_defs[] = { MSR_GLIU0_BASE1, MSR_GLIU0_BASE2,
+ MSR_GLIU0_BASE4, MSR_GLIU0_BASE5, MSR_GLIU0_BASE6,
+ GLIU0_P2D_BMO_0, GLIU0_P2D_BMO_1, MSR_GLIU0_SYSMEM,
+ GLIU0_P2D_RO_0, GLIU0_P2D_RO_1, GLIU0_P2D_RO_2,
+ MSR_GLIU0_SHADOW, GLIU0_IOD_BM_0, GLIU0_IOD_BM_1,
+ GLIU0_IOD_BM_2, GLIU0_IOD_SC_0, GLIU0_IOD_SC_1, GLIU0_IOD_SC_2,
+ GLIU0_IOD_SC_3, GLIU0_IOD_SC_4, GLIU0_IOD_SC_5,
+ GLIU0_GLD_MSR_COH, GL_END
+ };
+
+ int gliu1_msr_defs[] = { MSR_GLIU1_BASE1, MSR_GLIU1_BASE2,
+ MSR_GLIU1_BASE3, MSR_GLIU1_BASE4, MSR_GLIU1_BASE5,
+ MSR_GLIU1_BASE6, MSR_GLIU1_BASE7, MSR_GLIU1_BASE8,
+ MSR_GLIU1_BASE9, MSR_GLIU1_BASE10, GLIU1_P2D_R_0,
+ GLIU1_P2D_R_1, GLIU1_P2D_R_2, GLIU1_P2D_R_3, MSR_GLIU1_SHADOW,
+ GLIU1_IOD_BM_0, GLIU1_IOD_BM_1, GLIU1_IOD_BM_2, GLIU1_IOD_SC_0,
+ GLIU1_IOD_SC_1, GLIU1_IOD_SC_2, GLIU1_IOD_SC_3,
+ GLIU1_GLD_MSR_COH, GL_END
+ };
+
+ int rconf_msr[] = { CPU_RCONF0, CPU_RCONF1, CPU_RCONF2, CPU_RCONF3,
+ CPU_RCONF4, CPU_RCONF5, CPU_RCONF6, CPU_RCONF7, GL_END
+ };
+
+ int cs5536_msr[] = { MDD_LBAR_GPIO, MDD_LBAR_FLSH0, MDD_LBAR_FLSH1,
+ MDD_LEG_IO, MDD_PIN_OPT, MDD_IRQM_ZLOW, MDD_IRQM_ZHIGH,
+ MDD_IRQM_PRIM, GL_END
+ };
+
+ int pci_msr[] = { GLPCI_CTRL, GLPCI_ARB, GLPCI_REN, GLPCI_A0_BF,
+ GLPCI_C0_DF, GLPCI_E0_FF, GLPCI_RC0, GLPCI_RC1, GLPCI_RC2,
+ GLPCI_RC3, GLPCI_ExtMSR, GLPCI_SPARE, GL_END
+ };
+
+ int dma_msr[] = { MDD_DMA_MAP, MDD_DMA_SHAD1, MDD_DMA_SHAD2,
+ MDD_DMA_SHAD3, MDD_DMA_SHAD4, MDD_DMA_SHAD5, MDD_DMA_SHAD6,
+ MDD_DMA_SHAD7, MDD_DMA_SHAD8, MDD_DMA_SHAD9, GL_END
+ };
+
+ printk(BIOS_DEBUG, "---------- CPU ------------\n");
+
+ for (i = 0; cpu_msr_defs[i] != GL_END; i++) {
+ msr = rdmsr(cpu_msr_defs[i]);
+ printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n",
+ cpu_msr_defs[i], msr.hi, msr.lo);
+ }
+
+ printk(BIOS_DEBUG, "---------- GLIU 0 ------------\n");
+
+ for (i = 0; gliu0_msr_defs[i] != GL_END; i++) {
+ msr = rdmsr(gliu0_msr_defs[i]);
+ printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n",
+ gliu0_msr_defs[i], msr.hi, msr.lo);
+ }
+
+ printk(BIOS_DEBUG, "---------- GLIU 1 ------------\n");
+
+ for (i = 0; gliu1_msr_defs[i] != GL_END; i++) {
+ msr = rdmsr(gliu1_msr_defs[i]);
+ printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n",
+ gliu1_msr_defs[i], msr.hi, msr.lo);
+ }
+
+ printk(BIOS_DEBUG, "---------- RCONF ------------\n");
+
+ for (i = 0; rconf_msr[i] != GL_END; i++) {
+ msr = rdmsr(rconf_msr[i]);
+ printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", rconf_msr[i],
+ msr.hi, msr.lo);
+ }
+
+ printk(BIOS_DEBUG, "---------- VARIA ------------\n");
+ msr = rdmsr(0x51300010);
+ printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51300010, msr.hi,
+ msr.lo);
+
+ msr = rdmsr(0x51400015);
+ printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51400015, msr.hi,
+ msr.lo);
+
+ printk(BIOS_DEBUG, "---------- DIVIL IRQ ------------\n");
+ msr = rdmsr(MDD_IRQM_YLOW);
+ printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YLOW, msr.hi,
+ msr.lo);
+ msr = rdmsr(MDD_IRQM_YHIGH);
+ printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YHIGH,
+ msr.hi, msr.lo);
+ msr = rdmsr(MDD_IRQM_ZLOW);
+ printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZLOW, msr.hi,
+ msr.lo);
+ msr = rdmsr(MDD_IRQM_ZHIGH);
+ printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZHIGH,
+ msr.hi, msr.lo);
+
+ printk(BIOS_DEBUG, "---------- PCI ------------\n");
+
+ for (i = 0; pci_msr[i] != GL_END; i++) {
+ msr = rdmsr(pci_msr[i]);
+ printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", pci_msr[i],
+ msr.hi, msr.lo);
+ }
+
+ printk(BIOS_DEBUG, "---------- LPC/UART DMA ------------\n");
+
+ for (i = 0; dma_msr[i] != GL_END; i++) {
+ msr = rdmsr(dma_msr[i]);
+ printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", dma_msr[i],
+ msr.hi, msr.lo);
+ }
+
+ printk(BIOS_DEBUG, "---------- CS5536 ------------\n");
+
+ for (i = 0; cs5536_msr[i] != GL_END; i++) {
+ msr = rdmsr(cs5536_msr[i]);
+ printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", cs5536_msr[i],
+ msr.hi, msr.lo);
+ }
+
+ iol = inl(GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
+ printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n",
+ GPIO_IO_BASE + GPIOL_INPUT_ENABLE, iol);
+ iol = inl(GPIOL_EVENTS_ENABLE);
+ printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n",
+ GPIO_IO_BASE + GPIOL_EVENTS_ENABLE, iol);
+ iol = inl(GPIOL_INPUT_INVERT_ENABLE);
+ printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n",
+ GPIO_IO_BASE + GPIOL_INPUT_INVERT_ENABLE, iol);
+ iol = inl(GPIO_MAPPER_X);
+ printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n", GPIO_IO_BASE + GPIO_MAPPER_X,
+ iol);
+#endif //CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR
+}
+
+/* todo: add a resource record. We don't do this here because this may be called when
* very little of the platform is actually working.
*/
int sizeram(void)
int sizem = 0;
unsigned short dimm;
+ /* Get the RAM size from the memory controller as calculated and set by auto_size_dimm() */
msr = rdmsr(MC_CF07_DATA);
- printk_debug("sizeram: _MSR MC_CF07_DATA: %08x:%08x\n", msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "sizeram: _MSR MC_CF07_DATA: %08x:%08x\n", msr.hi, msr.lo);
/* dimm 0 */
dimm = msr.hi;
/* installed? */
if ((dimm & 7) != 7) {
- sizem = 4 << ((dimm >> 12) & 0x0F);
+ sizem = 4 << ((dimm >> 12) & 0x0F); /* 1:8MB, 2:16MB, 3:32MB, 4:64MB, ... 7:512MB, 8:1GB */
}
/* dimm 1 */
dimm = msr.hi >> 16;
/* installed? */
if ((dimm & 7) != 7) {
- sizem += 4 << ((dimm >> 12) & 0x0F);
+ sizem += 4 << ((dimm >> 12) & 0x0F); /* 1:8MB, 2:16MB, 3:32MB, 4:64MB, ... 7:512MB, 8:1GB */
}
- printk_debug("sizeram: sizem 0x%xMB\n", sizem);
+ printk(BIOS_DEBUG, "sizeram: sizem 0x%xMB\n", sizem);
return sizem;
}
{
//msr_t msr;
- printk_spew(">> Entering northbridge.c: %s\n", __FUNCTION__);
+ printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);
enable_shadow(dev);
/*
//msr.hi |= 0x3;
//msr.lo |= 0x30000;
- //printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU0_SHADOW, msr.hi, msr.lo);
- //printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU1_SHADOW, msr.hi, msr.lo);
+ //printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU0_SHADOW, msr.hi, msr.lo);
+ //printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU1_SHADOW, msr.hi, msr.lo);
}
-void northbridge_set_resources(struct device *dev)
+static void northbridge_set_resources(struct device *dev)
{
- struct resource *resource, *last;
- unsigned link;
uint8_t line;
- last = &dev->resource[dev->resources];
-
- for (resource = &dev->resource[0]; resource < last; resource++) {
+#if 0
+ struct resource *res;
+ for (res = dev->resource_list; res; res = res->next) {
// andrei: do not change the base address, it will make the VSA virtual registers unusable
- //pci_set_resource(dev, resource);
+ //pci_set_resource(dev, res);
// FIXME: static allocation may conflict with dynamic mappings!
}
+#endif
- for (link = 0; link < dev->links; link++) {
- struct bus *bus;
- bus = &dev->link[link];
+ struct bus *bus;
+ for (bus = dev->link_list; bus; bus = bus->next) {
if (bus->children) {
- printk_debug
- ("my_dev_set_resources: assign_resources %d\n",
- bus);
+ printk(BIOS_DEBUG, "my_dev_set_resources: assign_resources %d\n",
+ bus->secondary);
assign_resources(bus);
}
}
.ops_pci = 0,
};
-static struct pci_driver northbridge_driver __pci_driver = {
+static const struct pci_driver northbridge_driver __pci_driver = {
.ops = &northbridge_operations,
.vendor = PCI_VENDOR_ID_AMD,
.device = PCI_DEVICE_ID_AMD_LXBRIDGE,
};
-static void pci_domain_read_resources(device_t dev)
-{
- struct resource *resource;
- printk_spew(">> Entering northbridge.c: %s\n", __FUNCTION__);
-
- /* Initialize the system wide io space constraints */
- resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
- resource->limit = 0xffffUL;
- resource->flags =
- IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-
- /* Initialize the system wide memory resources constraints */
- resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
- resource->limit = 0xffffffffULL;
- resource->flags =
- IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-}
-
-static void ram_resource(device_t dev, unsigned long index,
- unsigned long basek, unsigned long sizek)
-{
- struct resource *resource;
-
- if (!sizek)
- return;
-
- resource = new_resource(dev, index);
- resource->base = ((resource_t) basek) << 10;
- resource->size = ((resource_t) sizek) << 10;
- resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE |
- IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
-}
+#if CONFIG_WRITE_HIGH_TABLES==1
+#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB
+extern uint64_t high_tables_base, high_tables_size;
+#endif
static void pci_domain_set_resources(device_t dev)
{
int idx;
+ u32 tomk;
device_t mc_dev;
- printk_spew(">> Entering northbridge.c: %s\n", __FUNCTION__);
+ printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);
- mc_dev = dev->link[0].children;
+ mc_dev = dev->link_list->children;
if (mc_dev) {
- /* Report the memory regions */
+ tomk = get_systop() / 1024;
+ /* Report the memory regions
+ All memory up to systop except 0xa0000-0xbffff */
idx = 10;
ram_resource(dev, idx++, 0, 640);
- ram_resource(dev, idx++, 1024, (get_systop() - 0x100000) / 1024); // Systop - 1 MB -> KB
+ ram_resource(dev, idx++, 768, tomk - 768); // Systop - 0xc0000 -> KB
+
+#if CONFIG_WRITE_HIGH_TABLES==1
+ /* Leave some space for ACPI, PIRQ and MP tables */
+ high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024;
+ high_tables_size = HIGH_TABLES_SIZE * 1024;
+#endif
}
- assign_resources(&dev->link[0]);
+ assign_resources(dev->link_list);
}
static void pci_domain_enable(device_t dev)
{
-
- printk_spew(">> Entering northbridge.c: %s\n", __FUNCTION__);
+ printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);
// do this here for now -- this chip really breaks our device model
northbridge_init_early();
cpubug();
chipsetinit();
- setup_realmode_idt();
-
- printk_debug("Before VSA:\n");
// print_conf();
do_vsmbios(); // do the magic stuff here, so prepare your tambourine ;)
- printk_debug("After VSA:\n");
// print_conf();
graphics_init();
pci_set_method(dev);
}
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
-{
- printk_spew(">> Entering northbridge.c: %s\n", __FUNCTION__);
-
- max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
- return max;
-}
-
static struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources,
- .enable_resources = enable_childrens_resources,
+ .enable_resources = NULL,
.scan_bus = pci_domain_scan_bus,
.enable = pci_domain_enable,
};
static void cpu_bus_init(device_t dev)
{
- printk_spew(">> Entering northbridge.c: %s\n", __FUNCTION__);
+ printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);
- initialize_cpus(&dev->link[0]);
+ initialize_cpus(dev->link_list);
}
static void cpu_bus_noop(device_t dev)
static void enable_dev(struct device *dev)
{
- printk_spew(">> Entering northbridge.c: %s with path %d\n",
- __FUNCTION__, dev->path.type);
+ printk(BIOS_SPEW, ">> Entering northbridge.c: %s with path %d\n",
+ __func__, dev->path.type);
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_PCI_DOMAIN)
projects / coreboot.git / blobdiff