#define IOD_BM(msr, pdid1, bizarro, ibase, imask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(ibase>>12), .lo=(ibase<<20)|imask}}
#define IOD_SC(msr, pdid1, bizarro, en, wen, ren, ibase) {msr, {.hi=(pdid1<<29)|(bizarro<<28), .lo=(en<<24)|(wen<<21)|(ren<<20)|(ibase<<3)}}
-extern void graphics_init(void);
-extern void cpubug(void);
-extern void chipsetinit(void);
-extern uint32_t get_systop(void);
-
-void northbridge_init_early(void);
-void setup_realmode_idt(void);
+void print_conf(void);
+void graphics_init(void);
void do_vsmbios(void);
struct msr_defaults {
MDD_DMA_SHAD7, MDD_DMA_SHAD8, MDD_DMA_SHAD9, GL_END
};
- printk_debug("---------- CPU ------------\n");
+ printk(BIOS_DEBUG, "---------- CPU ------------\n");
for (i = 0; cpu_msr_defs[i] != GL_END; i++) {
msr = rdmsr(cpu_msr_defs[i]);
- printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n",
+ printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n",
cpu_msr_defs[i], msr.hi, msr.lo);
}
- printk_debug("---------- GLIU 0 ------------\n");
+ printk(BIOS_DEBUG, "---------- GLIU 0 ------------\n");
for (i = 0; gliu0_msr_defs[i] != GL_END; i++) {
msr = rdmsr(gliu0_msr_defs[i]);
- printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n",
+ printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n",
gliu0_msr_defs[i], msr.hi, msr.lo);
}
- printk_debug("---------- GLIU 1 ------------\n");
+ printk(BIOS_DEBUG, "---------- GLIU 1 ------------\n");
for (i = 0; gliu1_msr_defs[i] != GL_END; i++) {
msr = rdmsr(gliu1_msr_defs[i]);
- printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n",
+ printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n",
gliu1_msr_defs[i], msr.hi, msr.lo);
}
- printk_debug("---------- RCONF ------------\n");
+ printk(BIOS_DEBUG, "---------- RCONF ------------\n");
for (i = 0; rconf_msr[i] != GL_END; i++) {
msr = rdmsr(rconf_msr[i]);
- printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", rconf_msr[i],
+ printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", rconf_msr[i],
msr.hi, msr.lo);
}
- printk_debug("---------- VARIA ------------\n");
+ printk(BIOS_DEBUG, "---------- VARIA ------------\n");
msr = rdmsr(0x51300010);
- printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51300010, msr.hi,
+ printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51300010, msr.hi,
msr.lo);
msr = rdmsr(0x51400015);
- printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51400015, msr.hi,
+ printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51400015, msr.hi,
msr.lo);
- printk_debug("---------- DIVIL IRQ ------------\n");
+ printk(BIOS_DEBUG, "---------- DIVIL IRQ ------------\n");
msr = rdmsr(MDD_IRQM_YLOW);
- printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YLOW, msr.hi,
+ printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YLOW, msr.hi,
msr.lo);
msr = rdmsr(MDD_IRQM_YHIGH);
- printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YHIGH,
+ printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YHIGH,
msr.hi, msr.lo);
msr = rdmsr(MDD_IRQM_ZLOW);
- printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZLOW, msr.hi,
+ printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZLOW, msr.hi,
msr.lo);
msr = rdmsr(MDD_IRQM_ZHIGH);
- printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZHIGH,
+ printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZHIGH,
msr.hi, msr.lo);
- printk_debug("---------- PCI ------------\n");
+ printk(BIOS_DEBUG, "---------- PCI ------------\n");
for (i = 0; pci_msr[i] != GL_END; i++) {
msr = rdmsr(pci_msr[i]);
- printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", pci_msr[i],
+ printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", pci_msr[i],
msr.hi, msr.lo);
}
- printk_debug("---------- LPC/UART DMA ------------\n");
+ printk(BIOS_DEBUG, "---------- LPC/UART DMA ------------\n");
for (i = 0; dma_msr[i] != GL_END; i++) {
msr = rdmsr(dma_msr[i]);
- printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", dma_msr[i],
+ printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", dma_msr[i],
msr.hi, msr.lo);
}
- printk_debug("---------- CS5536 ------------\n");
+ printk(BIOS_DEBUG, "---------- CS5536 ------------\n");
for (i = 0; cs5536_msr[i] != GL_END; i++) {
msr = rdmsr(cs5536_msr[i]);
- printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", cs5536_msr[i],
+ printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", cs5536_msr[i],
msr.hi, msr.lo);
}
iol = inl(GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
- printk_debug("IOR 0x%08X is now 0x%08X\n",
+ printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n",
GPIO_IO_BASE + GPIOL_INPUT_ENABLE, iol);
iol = inl(GPIOL_EVENTS_ENABLE);
- printk_debug("IOR 0x%08X is now 0x%08X\n",
+ printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n",
GPIO_IO_BASE + GPIOL_EVENTS_ENABLE, iol);
iol = inl(GPIOL_INPUT_INVERT_ENABLE);
- printk_debug("IOR 0x%08X is now 0x%08X\n",
+ printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n",
GPIO_IO_BASE + GPIOL_INPUT_INVERT_ENABLE, iol);
iol = inl(GPIO_MAPPER_X);
- printk_debug("IOR 0x%08X is now 0x%08X\n", GPIO_IO_BASE + GPIO_MAPPER_X,
+ printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n", GPIO_IO_BASE + GPIO_MAPPER_X,
iol);
#endif //CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR
}
-/* todo: add a resource record. We don't do this here because this may be called when
+/* todo: add a resource record. We don't do this here because this may be called when
* very little of the platform is actually working.
*/
int sizeram(void)
/* Get the RAM size from the memory controller as calculated and set by auto_size_dimm() */
msr = rdmsr(MC_CF07_DATA);
- printk_debug("sizeram: _MSR MC_CF07_DATA: %08x:%08x\n", msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "sizeram: _MSR MC_CF07_DATA: %08x:%08x\n", msr.hi, msr.lo);
/* dimm 0 */
dimm = msr.hi;
sizem += 4 << ((dimm >> 12) & 0x0F); /* 1:8MB, 2:16MB, 3:32MB, 4:64MB, ... 7:512MB, 8:1GB */
}
- printk_debug("sizeram: sizem 0x%xMB\n", sizem);
+ printk(BIOS_DEBUG, "sizeram: sizem 0x%xMB\n", sizem);
return sizem;
}
{
//msr_t msr;
- printk_spew(">> Entering northbridge.c: %s\n", __func__);
+ printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);
enable_shadow(dev);
/*
//msr.hi |= 0x3;
//msr.lo |= 0x30000;
- //printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU0_SHADOW, msr.hi, msr.lo);
- //printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU1_SHADOW, msr.hi, msr.lo);
+ //printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU0_SHADOW, msr.hi, msr.lo);
+ //printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU1_SHADOW, msr.hi, msr.lo);
}
-void northbridge_set_resources(struct device *dev)
+static void northbridge_set_resources(struct device *dev)
{
- struct resource *resource, *last;
- unsigned link;
uint8_t line;
- last = &dev->resource[dev->resources];
-
- for (resource = &dev->resource[0]; resource < last; resource++) {
+#if 0
+ struct resource *res;
+ for (res = dev->resource_list; res; res = res->next) {
// andrei: do not change the base address, it will make the VSA virtual registers unusable
- //pci_set_resource(dev, resource);
+ //pci_set_resource(dev, res);
// FIXME: static allocation may conflict with dynamic mappings!
}
+#endif
- for (link = 0; link < dev->links; link++) {
- struct bus *bus;
- bus = &dev->link[link];
+ struct bus *bus;
+ for (bus = dev->link_list; bus; bus = bus->next) {
if (bus->children) {
- printk_debug
- ("my_dev_set_resources: assign_resources %d\n",
- bus);
+ printk(BIOS_DEBUG, "my_dev_set_resources: assign_resources %d\n",
+ bus->secondary);
assign_resources(bus);
}
}
.device = PCI_DEVICE_ID_AMD_LXBRIDGE,
};
-static void ram_resource(device_t dev, unsigned long index,
- unsigned long basek, unsigned long sizek)
-{
- struct resource *resource;
-
- if (!sizek)
- return;
-
- resource = new_resource(dev, index);
- resource->base = ((resource_t) basek) << 10;
- resource->size = ((resource_t) sizek) << 10;
- resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE |
- IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
-}
-
#if CONFIG_WRITE_HIGH_TABLES==1
#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB
extern uint64_t high_tables_base, high_tables_size;
u32 tomk;
device_t mc_dev;
- printk_spew(">> Entering northbridge.c: %s\n", __func__);
+ printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);
- mc_dev = dev->link[0].children;
+ mc_dev = dev->link_list->children;
if (mc_dev) {
tomk = get_systop() / 1024;
/* Report the memory regions
#endif
}
- assign_resources(&dev->link[0]);
+ assign_resources(dev->link_list);
}
static void pci_domain_enable(device_t dev)
{
-
- printk_spew(">> Entering northbridge.c: %s\n", __func__);
+ printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);
// do this here for now -- this chip really breaks our device model
northbridge_init_early();
cpubug();
chipsetinit();
- setup_realmode_idt();
-
- printk_debug("Before VSA:\n");
// print_conf();
do_vsmbios(); // do the magic stuff here, so prepare your tambourine ;)
- printk_debug("After VSA:\n");
// print_conf();
graphics_init();
static struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources,
- .enable_resources = enable_childrens_resources,
+ .enable_resources = NULL,
.scan_bus = pci_domain_scan_bus,
.enable = pci_domain_enable,
};
static void cpu_bus_init(device_t dev)
{
- printk_spew(">> Entering northbridge.c: %s\n", __func__);
+ printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);
- initialize_cpus(&dev->link[0]);
+ initialize_cpus(dev->link_list);
}
static void cpu_bus_noop(device_t dev)
static void enable_dev(struct device *dev)
{
- printk_spew(">> Entering northbridge.c: %s with path %d\n",
+ printk(BIOS_SPEW, ">> Entering northbridge.c: %s with path %d\n",
__func__, dev->path.type);
/* Set the operations if it is a special bus type */
projects / coreboot.git / blobdiff