+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
#include <console/console.h>
#include <arch/io.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <bitops.h>
-#include "chip.h"
-#include "northbridge.h"
#include <cpu/cpu.h>
#include <cpu/amd/lxdef.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/cache.h>
#include <cpu/amd/vr.h>
-#define VIDEO_MB 8
-
-extern void graphics_init(void);
-
-#define NORTHBRIDGE_FILE "northbridge.c"
-
-/* todo: add a resource record. We don't do this here because this may be called when
- * very little of the platform is actually working.
- */
-int
-sizeram(void)
-{
- msr_t msr;
- int sizem = 0;
- unsigned short dimm;
-
- msr = rdmsr(0x20000018);
- printk_debug("sizeram: %08x:%08x\n", msr.hi, msr.lo);
-
- /* dimm 0 */
- dimm = msr.hi;
- /* installed? */
- if ((dimm & 7) != 7)
- sizem = (1 << ((dimm >> 12)-1)) * 8;
-
-
- /* dimm 1*/
- dimm = msr.hi >> 16;
- /* installed? */
- if ((dimm & 7) != 7)
- sizem += (1 << ((dimm >> 12)-1)) * 8;
-
- printk_debug("sizeram: sizem 0x%x\n", sizem);
- return sizem;
-}
+#include <cpu/cpu.h>
+#include "chip.h"
+#include "northbridge.h"
+#include "../../../southbridge/amd/cs5536/cs5536.h"
/* here is programming for the various MSRs.*/
#define IM_QWAIT 0x100000
-#define DMCF_WRITE_SERIALIZE_REQUEST (2<<12) /* 2 outstanding */ /* in high */
-#define DMCF_SERIAL_LOAD_MISSES (2) /* enabled */
+#define DMCF_WRITE_SERIALIZE_REQUEST (2<<12) /* 2 outstanding */ /* in high */
+#define DMCF_SERIAL_LOAD_MISSES (2) /* enabled */
/* these are the 8-bit attributes for controlling RCONF registers */
#define CACHE_DISABLE (1<<0)
#define IOD_BM(msr, pdid1, bizarro, ibase, imask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(ibase>>12), .lo=(ibase<<20)|imask}}
#define IOD_SC(msr, pdid1, bizarro, en, wen, ren, ibase) {msr, {.hi=(pdid1<<29)|(bizarro<<28), .lo=(en<<24)|(wen<<21)|(ren<<20)|(ibase<<3)}}
-
+void print_conf(void);
+void graphics_init(void);
+void do_vsmbios(void);
struct msr_defaults {
int msr_no;
msr_t msr;
-} msr_defaults [] = {
- {0x1700, {.hi = 0, .lo = IM_QWAIT}},
- {0x1800, {.hi = DMCF_WRITE_SERIALIZE_REQUEST, .lo = DMCF_SERIAL_LOAD_MISSES}},
- /* 1808 will be done down below, so we have to do 180a->1817 (well, 1813 really) */
- /* for 180a, for now, we assume VSM will configure it */
- /* 180b is left at reset value,a0000-bffff is non-cacheable */
- /* 180c, c0000-dffff is set to write serialize and non-cachable */
- /* oops, 180c will be set by cpu bug handling in cpubug.c */
- //{0x180c, {.hi = MSR_WS_CD_DEFAULT, .lo = MSR_WS_CD_DEFAULT}},
- /* 180d is left at default, e0000-fffff is non-cached */
-
- /* we will assume 180e, the ssm region configuration, is left at default or set by VSM */
- /* we will not set 0x180f, the DMM,yet */
- //{0x1810, {.hi=0xee7ff000, .lo=RRCF_LOW(0xee000000, WRITE_COMBINE|CACHE_DISABLE)}},
- //{0x1811, {.hi = 0xefffb000, .lo = RRCF_LOW_CD(0xefff8000)}},
- //{0x1812, {.hi = 0xefff7000, .lo = RRCF_LOW_CD(0xefff4000)}},
- //{0x1813, {.hi = 0xefff3000, .lo = RRCF_LOW_CD(0xefff0000)}},
- /* now for GLPCI routing */
- /* GLIU0 */
- P2D_BM(0x10000020, 0x1, 0x0, 0x0, 0xfff80),
- P2D_BM(0x10000021, 0x1, 0x0, 0x80000, 0xfffe0),
- P2D_SC(0x1000002c, 0x1, 0x0, 0x0, 0xff03, 0xC0000),
- /* GLIU1 */
- P2D_BM(0x40000020, 0x1, 0x0, 0x0, 0xfff80),
- P2D_BM(0x40000021, 0x1, 0x0, 0x80000, 0xfffe0),
- P2D_SC(0x4000002e, 0x1, 0x0, 0x0, 0xff03, 0xC0000), // GX3 0x4000002d -> 0x4000002e
- {0}
+} msr_defaults[] = {
+ {
+ 0x1700, {
+ .hi = 0,.lo = IM_QWAIT}}, {
+ 0x1800, {
+ .hi = DMCF_WRITE_SERIALIZE_REQUEST,.lo =
+ DMCF_SERIAL_LOAD_MISSES}},
+ /* 1808 will be done down below, so we have to do 180a->1817 (well, 1813 really) */
+ /* for 180a, for now, we assume VSM will configure it */
+ /* 180b is left at reset value,a0000-bffff is non-cacheable */
+ /* 180c, c0000-dffff is set to write serialize and non-cachable */
+ /* oops, 180c will be set by cpu bug handling in cpubug.c */
+ //{0x180c, {.hi = MSR_WS_CD_DEFAULT, .lo = MSR_WS_CD_DEFAULT}},
+ /* 180d is left at default, e0000-fffff is non-cached */
+ /* we will assume 180e, the ssm region configuration, is left at default or set by VSM */
+ /* we will not set 0x180f, the DMM,yet */
+ //{0x1810, {.hi=0xee7ff000, .lo=RRCF_LOW(0xee000000, WRITE_COMBINE|CACHE_DISABLE)}},
+ //{0x1811, {.hi = 0xefffb000, .lo = RRCF_LOW_CD(0xefff8000)}},
+ //{0x1812, {.hi = 0xefff7000, .lo = RRCF_LOW_CD(0xefff4000)}},
+ //{0x1813, {.hi = 0xefff3000, .lo = RRCF_LOW_CD(0xefff0000)}},
+ /* now for GLPCI routing */
+ /* GLIU0 */
+ P2D_BM(MSR_GLIU0_BASE1, 0x1, 0x0, 0x0, 0xfff80),
+ P2D_BM(MSR_GLIU0_BASE2, 0x1, 0x0, 0x80000, 0xfffe0),
+ P2D_SC(MSR_GLIU0_SHADOW, 0x1, 0x0, 0x0, 0xff03, 0xC0000),
+ /* GLIU1 */
+ P2D_BM(MSR_GLIU1_BASE1, 0x1, 0x0, 0x0, 0xfff80),
+ P2D_BM(MSR_GLIU1_BASE2, 0x1, 0x0, 0x80000, 0xfffe0),
+ P2D_SC(MSR_GLIU1_SHADOW, 0x1, 0x0, 0x0, 0xff03, 0xC0000), {
+ 0}
};
-/* note that dev is NOT used -- yet */
-static void irq_init_steering(struct device *dev, uint16_t irq_map) {
- /* Set up IRQ steering */
- uint32_t pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
-
- printk_debug("%s(%08X [%08X], %04X)\n", __FUNCTION__, dev, pciAddr, irq_map);
-
- /* The IRQ steering values (in hex) are effectively dcba, where:
- * <a> represents the IRQ for INTA,
- * <b> represents the IRQ for INTB,
- * <c> represents the IRQ for INTC, and
- * <d> represents the IRQ for INTD.
- * Thus, a value of irq_map = 0xAA5B translates to:
- * INTA = IRQB (IRQ 11)
- * INTB = IRQ5 (IRQ 5)
- * INTC = IRQA (IRQ 10)
- * INTD = IRQA (IRQ 10)
- */
- outl(pciAddr & ~3, 0xCF8);
- outl(irq_map, 0xCFC);
-}
-
-
-/*
- * setup_lx_cache
- *
- * Returns the amount of memory (in KB) available to the system. This is the
- * total amount of memory less the amount of memory reserved for SMM use.
- *
- */
-static int
-setup_lx_cache(void)
+/* Print the platform configuration - do before PCI init or it will not
+ * work right.
+ */
+void print_conf(void)
{
+#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR
+ int i;
+ unsigned long iol;
msr_t msr;
- unsigned long long val;
- int sizekbytes, sizereg;
-
- sizekbytes = sizeram() * 1024;
- printk_debug("setup_lx_cache: enable for %d KB\n", sizekbytes);
- /* build up the rconf word. */
- /* the SYSTOP bits 27:8 are actually the top bits from 31:12. Book fails to say that */
- /* set romrp */
- val = ((unsigned long long) ROM_PROPERTIES) << 56;
- /* make rom base useful for 1M roms */
- /* Flash base address -- sized for 1M for now*/
- val |= ((unsigned long long) 0xfff00)<<36;
- /* set the devrp properties */
- val |= ((unsigned long long) DEVICE_PROPERTIES) << 28;
- /* Take our TOM, RIGHT shift 12, since it page-aligned, then LEFT-shift 8 for reg. */
- /* yank off memory for the SMM handler */
- sizekbytes -= SMM_SIZE;
- sizereg = sizekbytes;
- sizereg *= 1024; // convert to bytes
- sizereg >>= 12;
- sizereg <<= 8;
- val |= sizereg;
- val |= RAM_PROPERTIES;
- msr.lo = val;
- msr.hi = (val >> 32);
- printk_debug("msr 0x%08X will be set to %08x:%08x\n", CPU_RCONF_DEFAULT, msr.hi, msr.lo);
- wrmsr(CPU_RCONF_DEFAULT, msr);
-
- enable_cache();
- wbinvd();
- return sizekbytes;
-}
-/* we have to do this here. We have not found a nicer way to do it */
-void
-setup_lx(void)
-{
+ int cpu_msr_defs[] = { CPU_BC_L2_CONF, CPU_IM_CONFIG, CPU_DM_CONFIG0,
+ CPU_RCONF_DEFAULT, CPU_RCONF_BYPASS, CPU_RCONF_A0_BF,
+ CPU_RCONF_C0_DF, CPU_RCONF_E0_FF, CPU_RCONF_SMM, CPU_RCONF_DMM,
+ GLCP_DELAY_CONTROLS, GL_END
+ };
+
+ int gliu0_msr_defs[] = { MSR_GLIU0_BASE1, MSR_GLIU0_BASE2,
+ MSR_GLIU0_BASE4, MSR_GLIU0_BASE5, MSR_GLIU0_BASE6,
+ GLIU0_P2D_BMO_0, GLIU0_P2D_BMO_1, MSR_GLIU0_SYSMEM,
+ GLIU0_P2D_RO_0, GLIU0_P2D_RO_1, GLIU0_P2D_RO_2,
+ MSR_GLIU0_SHADOW, GLIU0_IOD_BM_0, GLIU0_IOD_BM_1,
+ GLIU0_IOD_BM_2, GLIU0_IOD_SC_0, GLIU0_IOD_SC_1, GLIU0_IOD_SC_2,
+ GLIU0_IOD_SC_3, GLIU0_IOD_SC_4, GLIU0_IOD_SC_5,
+ GLIU0_GLD_MSR_COH, GL_END
+ };
+
+ int gliu1_msr_defs[] = { MSR_GLIU1_BASE1, MSR_GLIU1_BASE2,
+ MSR_GLIU1_BASE3, MSR_GLIU1_BASE4, MSR_GLIU1_BASE5,
+ MSR_GLIU1_BASE6, MSR_GLIU1_BASE7, MSR_GLIU1_BASE8,
+ MSR_GLIU1_BASE9, MSR_GLIU1_BASE10, GLIU1_P2D_R_0,
+ GLIU1_P2D_R_1, GLIU1_P2D_R_2, GLIU1_P2D_R_3, MSR_GLIU1_SHADOW,
+ GLIU1_IOD_BM_0, GLIU1_IOD_BM_1, GLIU1_IOD_BM_2, GLIU1_IOD_SC_0,
+ GLIU1_IOD_SC_1, GLIU1_IOD_SC_2, GLIU1_IOD_SC_3,
+ GLIU1_GLD_MSR_COH, GL_END
+ };
+
+ int rconf_msr[] = { CPU_RCONF0, CPU_RCONF1, CPU_RCONF2, CPU_RCONF3,
+ CPU_RCONF4, CPU_RCONF5, CPU_RCONF6, CPU_RCONF7, GL_END
+ };
+
+ int cs5536_msr[] = { MDD_LBAR_GPIO, MDD_LBAR_FLSH0, MDD_LBAR_FLSH1,
+ MDD_LEG_IO, MDD_PIN_OPT, MDD_IRQM_ZLOW, MDD_IRQM_ZHIGH,
+ MDD_IRQM_PRIM, GL_END
+ };
+
+ int pci_msr[] = { GLPCI_CTRL, GLPCI_ARB, GLPCI_REN, GLPCI_A0_BF,
+ GLPCI_C0_DF, GLPCI_E0_FF, GLPCI_RC0, GLPCI_RC1, GLPCI_RC2,
+ GLPCI_RC3, GLPCI_ExtMSR, GLPCI_SPARE, GL_END
+ };
+
+ int dma_msr[] = { MDD_DMA_MAP, MDD_DMA_SHAD1, MDD_DMA_SHAD2,
+ MDD_DMA_SHAD3, MDD_DMA_SHAD4, MDD_DMA_SHAD5, MDD_DMA_SHAD6,
+ MDD_DMA_SHAD7, MDD_DMA_SHAD8, MDD_DMA_SHAD9, GL_END
+ };
+
+ printk(BIOS_DEBUG, "---------- CPU ------------\n");
+
+ for (i = 0; cpu_msr_defs[i] != GL_END; i++) {
+ msr = rdmsr(cpu_msr_defs[i]);
+ printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n",
+ cpu_msr_defs[i], msr.hi, msr.lo);
+ }
- unsigned long tmp, tmp2;
- msr_t msr;
- unsigned long size_kb, membytes;
+ printk(BIOS_DEBUG, "---------- GLIU 0 ------------\n");
- size_kb = setup_lx_cache();
+ for (i = 0; gliu0_msr_defs[i] != GL_END; i++) {
+ msr = rdmsr(gliu0_msr_defs[i]);
+ printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n",
+ gliu0_msr_defs[i], msr.hi, msr.lo);
+ }
- membytes = size_kb * 1024;
- /* NOTE! setup_lx_cache returns the SIZE OF RAM - RAMADJUST!
- * so it is safe to use. You should NOT at this point call
- * sizeram() directly.
- */
+ printk(BIOS_DEBUG, "---------- GLIU 1 ------------\n");
- /* we need to set 0x10000028 and 0x40000029 */
- /*
- * These two descriptors cover the range from 1 MB (0x100000) to
- * SYSTOP (a.k.a. TOM, or Top of Memory)
- */
+ for (i = 0; gliu1_msr_defs[i] != GL_END; i++) {
+ msr = rdmsr(gliu1_msr_defs[i]);
+ printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n",
+ gliu1_msr_defs[i], msr.hi, msr.lo);
+ }
-#if 0
- /* This has already been done elsewhere */
- printk_debug("size_kb 0x%x, membytes 0x%x\n", size_kb, membytes);
- msr.hi = 0x20000000 | membytes>>24;
- msr.lo = 0x100 | ( ((membytes >>12) & 0xfff) << 20);
- wrmsr(0x10000028, msr);
- msr.hi = 0x20000000 | membytes>>24;
- msr.lo = 0x100 | ( ((membytes >>12) & 0xfff) << 20);
- wrmsr(0x40000029, msr);
-#endif
-#if 0
- msr = rdmsr(0x10000028);
- printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000028, msr.hi,msr.lo);
- msr = rdmsr(0x40000029);
- printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x40000029, msr.hi,msr.lo);
-#endif
-#if 1
- /* fixme: SMM MSR 0x10000026 and 0x400000023 */
- /* calculate the OFFSET field */
- tmp = membytes - SMM_OFFSET;
- tmp >>= 12;
- tmp <<= 8;
- tmp |= 0x20000000;
- tmp |= (SMM_OFFSET >> 24);
-
- /* calculate the PBASE and PMASK fields */
- tmp2 = (SMM_OFFSET << 8) & 0xFFF00000; /* shift right 12 then left 20 == left 8 */
- tmp2 |= (((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff);
- printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000026, tmp, tmp2);
- msr.hi = tmp;
- msr.lo = tmp2;
- wrmsr(0x10000026, msr);
-#endif
-#if 0
+ printk(BIOS_DEBUG, "---------- RCONF ------------\n");
- msr.hi = 0x2cfbc040;
- msr.lo = 0x400fffc0;
- wrmsr(0x10000026, msr);
- msr = rdmsr(0x10000026);
- printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000026, msr.hi, msr.lo);
-#endif
-#if 0
- msr.hi = 0x22fffc02;
- msr.lo = 0x10ffbf00;
- wrmsr(0x1808, msr);
- msr = rdmsr(0x1808);
- printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x1808, msr.hi, msr.lo);
-#endif
-#if 0 // SDG - don't do this
- /* now do the default MSR values */
- for(i = 0; msr_defaults[i].msr_no; i++) {
- msr_t msr;
- wrmsr(msr_defaults[i].msr_no, msr_defaults[i].msr); // MSR - see table above
- msr = rdmsr(msr_defaults[i].msr_no);
- printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", msr_defaults[i].msr_no, msr.hi,msr.lo);
+ for (i = 0; rconf_msr[i] != GL_END; i++) {
+ msr = rdmsr(rconf_msr[i]);
+ printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", rconf_msr[i],
+ msr.hi, msr.lo);
}
-#endif
+
+ printk(BIOS_DEBUG, "---------- VARIA ------------\n");
+ msr = rdmsr(0x51300010);
+ printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51300010, msr.hi,
+ msr.lo);
+
+ msr = rdmsr(0x51400015);
+ printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51400015, msr.hi,
+ msr.lo);
+
+ printk(BIOS_DEBUG, "---------- DIVIL IRQ ------------\n");
+ msr = rdmsr(MDD_IRQM_YLOW);
+ printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YLOW, msr.hi,
+ msr.lo);
+ msr = rdmsr(MDD_IRQM_YHIGH);
+ printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YHIGH,
+ msr.hi, msr.lo);
+ msr = rdmsr(MDD_IRQM_ZLOW);
+ printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZLOW, msr.hi,
+ msr.lo);
+ msr = rdmsr(MDD_IRQM_ZHIGH);
+ printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZHIGH,
+ msr.hi, msr.lo);
+
+ printk(BIOS_DEBUG, "---------- PCI ------------\n");
+
+ for (i = 0; pci_msr[i] != GL_END; i++) {
+ msr = rdmsr(pci_msr[i]);
+ printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", pci_msr[i],
+ msr.hi, msr.lo);
+ }
+
+ printk(BIOS_DEBUG, "---------- LPC/UART DMA ------------\n");
+
+ for (i = 0; dma_msr[i] != GL_END; i++) {
+ msr = rdmsr(dma_msr[i]);
+ printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", dma_msr[i],
+ msr.hi, msr.lo);
+ }
+
+ printk(BIOS_DEBUG, "---------- CS5536 ------------\n");
+
+ for (i = 0; cs5536_msr[i] != GL_END; i++) {
+ msr = rdmsr(cs5536_msr[i]);
+ printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", cs5536_msr[i],
+ msr.hi, msr.lo);
+ }
+
+ iol = inl(GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
+ printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n",
+ GPIO_IO_BASE + GPIOL_INPUT_ENABLE, iol);
+ iol = inl(GPIOL_EVENTS_ENABLE);
+ printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n",
+ GPIO_IO_BASE + GPIOL_EVENTS_ENABLE, iol);
+ iol = inl(GPIOL_INPUT_INVERT_ENABLE);
+ printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n",
+ GPIO_IO_BASE + GPIOL_INPUT_INVERT_ENABLE, iol);
+ iol = inl(GPIO_MAPPER_X);
+ printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n", GPIO_IO_BASE + GPIO_MAPPER_X,
+ iol);
+#endif //CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR
+}
+
+/* todo: add a resource record. We don't do this here because this may be called when
+ * very little of the platform is actually working.
+ */
+int sizeram(void)
+{
+ msr_t msr;
+ int sizem = 0;
+ unsigned short dimm;
+
+ /* Get the RAM size from the memory controller as calculated and set by auto_size_dimm() */
+ msr = rdmsr(MC_CF07_DATA);
+ printk(BIOS_DEBUG, "sizeram: _MSR MC_CF07_DATA: %08x:%08x\n", msr.hi, msr.lo);
+
+ /* dimm 0 */
+ dimm = msr.hi;
+ /* installed? */
+ if ((dimm & 7) != 7) {
+ sizem = 4 << ((dimm >> 12) & 0x0F); /* 1:8MB, 2:16MB, 3:32MB, 4:64MB, ... 7:512MB, 8:1GB */
+ }
+
+ /* dimm 1 */
+ dimm = msr.hi >> 16;
+ /* installed? */
+ if ((dimm & 7) != 7) {
+ sizem += 4 << ((dimm >> 12) & 0x0F); /* 1:8MB, 2:16MB, 3:32MB, 4:64MB, ... 7:512MB, 8:1GB */
+ }
+
+ printk(BIOS_DEBUG, "sizeram: sizem 0x%xMB\n", sizem);
+ return sizem;
}
static void enable_shadow(device_t dev)
{
-
}
+static void northbridge_init(device_t dev)
+{
+ //msr_t msr;
-static void enable_L2_cache(void) {
- msr_t msr;
+ printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);
- /* Instruction Memory Configuration register
- * set EBE bit, required when L2 cache is enabled
- */
- msr = rdmsr(CPU_IM_CONFIG);
- msr.lo |= 0x400;
- wrmsr(CPU_IM_CONFIG, msr);
-
- /* Data Memory Subsystem Configuration register
- * set EVCTONRPL bit, required when L2 cache is enabled in victim mode
+ enable_shadow(dev);
+ /*
+ * Swiss cheese
*/
- msr = rdmsr(CPU_DM_CONFIG0);
- msr.lo |= 0x4000;
- wrmsr(CPU_DM_CONFIG0, msr);
-
- /* invalidate L2 cache */
- msr.hi = 0x00;
- msr.lo = 0x10;
- wrmsr(L2_CONFIG_MSR, msr);
-
- /* Enable L2 cache */
- msr.hi = 0x00;
- msr.lo = 0x0f;
- wrmsr(L2_CONFIG_MSR, msr);
-
- printk_debug("L2 cache enabled\n");
-}
+ //msr = rdmsr(MSR_GLIU0_SHADOW);
+ //msr.hi |= 0x3;
+ //msr.lo |= 0x30000;
+
+ //printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU0_SHADOW, msr.hi, msr.lo);
+ //printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU1_SHADOW, msr.hi, msr.lo);
+}
-static void northbridge_init(device_t dev)
+static void northbridge_set_resources(struct device *dev)
{
- struct northbridge_amd_lx_config *nb = (struct northbridge_amd_lx_config *)dev->chip_info;
- printk_debug("northbridge: %s()\n", __FUNCTION__);
-
- enable_shadow(dev);
- irq_init_steering(dev, nb->irqmap);
+ uint8_t line;
+
+#if 0
+ struct resource *res;
+ for (res = dev->resource_list; res; res = res->next) {
+
+ // andrei: do not change the base address, it will make the VSA virtual registers unusable
+ //pci_set_resource(dev, res);
+ // FIXME: static allocation may conflict with dynamic mappings!
+ }
+#endif
+
+ struct bus *bus;
+ for (bus = dev->link_list; bus; bus = bus->next) {
+ if (bus->children) {
+ printk(BIOS_DEBUG, "my_dev_set_resources: assign_resources %d\n",
+ bus->secondary);
+ assign_resources(bus);
+ }
+ }
+
+ /* set a default latency timer */
+ pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
+
+ /* set a default secondary latency timer */
+ if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {
+ pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40);
+ }
+
+ /* zero the irq settings */
+ line = pci_read_config8(dev, PCI_INTERRUPT_PIN);
+ if (line) {
+ pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
+ }
+
+ /* set the cache line size, so far 64 bytes is good for everyone */
+ pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2);
}
static struct device_operations northbridge_operations = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
+ .read_resources = pci_dev_read_resources,
+ .set_resources = northbridge_set_resources,
.enable_resources = pci_dev_enable_resources,
- .init = northbridge_init,
- .enable = 0,
- .ops_pci = 0,
+ .init = northbridge_init,
+ .enable = 0,
+ .ops_pci = 0,
};
-static struct pci_driver northbridge_driver __pci_driver = {
+static const struct pci_driver northbridge_driver __pci_driver = {
.ops = &northbridge_operations,
.vendor = PCI_VENDOR_ID_AMD,
- .device = PCI_DEVICE_ID_AMD_LX,
+ .device = PCI_DEVICE_ID_AMD_LXBRIDGE,
};
-#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
+#if CONFIG_WRITE_HIGH_TABLES==1
+#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB
+extern uint64_t high_tables_base, high_tables_size;
+#endif
-static void pci_domain_read_resources(device_t dev)
+static void pci_domain_set_resources(device_t dev)
{
- struct resource *resource;
-
- printk_spew("%s:%s()\n", NORTHBRIDGE_FILE, __FUNCTION__);
-
- /* Initialize the system wide io space constraints */
- resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
- resource->limit = 0xffffUL;
- resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+ int idx;
+ u32 tomk;
+ device_t mc_dev;
- /* Initialize the system wide memory resources constraints */
- resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
- resource->limit = 0xffffffffULL;
- resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-}
+ printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);
-static void ram_resource(device_t dev, unsigned long index,
- unsigned long basek, unsigned long sizek)
-{
- struct resource *resource;
-
- if (!sizek) {
- return;
- }
- resource = new_resource(dev, index);
- resource->base = ((resource_t)basek) << 10;
- resource->size = ((resource_t)sizek) << 10;
- resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
- IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
-}
+ mc_dev = dev->link_list->children;
+ if (mc_dev) {
+ tomk = get_systop() / 1024;
+ /* Report the memory regions
+ All memory up to systop except 0xa0000-0xbffff */
+ idx = 10;
+ ram_resource(dev, idx++, 0, 640);
+ ram_resource(dev, idx++, 768, tomk - 768); // Systop - 0xc0000 -> KB
-static void tolm_test(void *gp, struct device *dev, struct resource *new)
-{
- struct resource **best_p = gp;
- struct resource *best;
- best = *best_p;
- if (!best || (best->base > new->base)) {
- best = new;
+#if CONFIG_WRITE_HIGH_TABLES==1
+ /* Leave some space for ACPI, PIRQ and MP tables */
+ high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024;
+ high_tables_size = HIGH_TABLES_SIZE * 1024;
+#endif
}
- *best_p = best;
-}
-#if 0
-static uint32_t find_pci_tolm(struct bus *bus)
-{
- struct resource *min;
- uint32_t tolm;
- min = 0;
- search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
- tolm = 0xffffffffUL;
- if (min && tolm > min->base) {
- tolm = min->base;
- }
- return tolm;
+ assign_resources(dev->link_list);
}
-#endif
-#define FRAMEBUFFERK 4096
-static void pci_domain_set_resources(device_t dev)
+static void pci_domain_enable(device_t dev)
{
-#if 0
- device_t mc_dev;
- uint32_t pci_tolm;
+ printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);
- pci_tolm = find_pci_tolm(&dev->link[0]);
- mc_dev = dev->link[0].children;
- if (mc_dev) {
- unsigned int tomk, tolmk;
- unsigned int ramreg = 0;
- int i, idx;
- unsigned int *bcdramtop = (unsigned int *)(GX_BASE + BC_DRAM_TOP);
- unsigned int *mcgbaseadd = (unsigned int *)(GX_BASE + MC_GBASE_ADD);
-
- for(i=0; i<0x20; i+= 0x10) {
- unsigned int *mcreg = (unsigned int *)(GX_BASE + MC_BANK_CFG);
- unsigned int mem_config = *mcreg;
-
- if (((mem_config & (DIMM_PG_SZ << i)) >> (4 + i)) == 7)
- continue;
- ramreg += 1 << (((mem_config & (DIMM_SZ << i)) >> (i + 8)) + 2);
- }
-
- tomk = ramreg << 10;
+ // do this here for now -- this chip really breaks our device model
+ northbridge_init_early();
+ cpubug();
+ chipsetinit();
- /* Sort out the framebuffer size */
- tomk -= FRAMEBUFFERK;
- *bcdramtop = ((tomk << 10) - 1);
- *mcgbaseadd = (tomk >> 9);
+ // print_conf();
- printk_debug("BC_DRAM_TOP = 0x%08x\n", *bcdramtop);
- printk_debug("MC_GBASE_ADD = 0x%08x\n", *mcgbaseadd);
+ do_vsmbios(); // do the magic stuff here, so prepare your tambourine ;)
- printk_debug("I would set ram size to %d Mbytes\n", (tomk >> 10));
+ // print_conf();
- /* Compute the top of Low memory */
- tolmk = pci_tolm >> 10;
- if (tolmk >= tomk) {
- /* The PCI hole does does not overlap the memory.
- */
- tolmk = tomk;
- }
- /* Report the memory regions */
- idx = 10;
- ram_resource(dev, idx++, 0, tolmk);
- }
-#endif
- assign_resources(&dev->link[0]);
-}
-
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
-{
- max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
- return max;
+ graphics_init();
+ pci_set_method(dev);
}
static struct device_operations pci_domain_ops = {
- .read_resources = pci_domain_read_resources,
- .set_resources = pci_domain_set_resources,
- .enable_resources = enable_childrens_resources,
- .init = 0,
- .scan_bus = pci_domain_scan_bus,
-};
+ .read_resources = pci_domain_read_resources,
+ .set_resources = pci_domain_set_resources,
+ .enable_resources = NULL,
+ .scan_bus = pci_domain_scan_bus,
+ .enable = pci_domain_enable,
+};
static void cpu_bus_init(device_t dev)
{
- initialize_cpus(&dev->link[0]);
+ printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);
+
+ initialize_cpus(dev->link_list);
}
static void cpu_bus_noop(device_t dev)
}
static struct device_operations cpu_bus_ops = {
- .read_resources = cpu_bus_noop,
- .set_resources = cpu_bus_noop,
- .enable_resources = cpu_bus_noop,
- .init = cpu_bus_init,
- .scan_bus = 0,
+ .read_resources = cpu_bus_noop,
+ .set_resources = cpu_bus_noop,
+ .enable_resources = cpu_bus_noop,
+ .init = cpu_bus_init,
+ .scan_bus = 0,
};
-void chipsetInit (void);
-
static void enable_dev(struct device *dev)
{
- printk_debug("lx north: enable_dev\n");
- void northbridgeinit(void);
- void chipsetinit(struct northbridge_amd_lx_config *nb);
- void setup_realmode_idt(void);
- void do_vsmbios(void);
- /* Set the operations if it is a special bus type */
- if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
- struct northbridge_amd_lx_config *nb = (struct northbridge_amd_lx_config *)dev->chip_info;
- extern void cpubug(void);
- printk_debug("DEVICE_PATH_PCI_DOMAIN\n");
- /* cpubug MUST be called before setup_lx(), so we force the issue here */
- enable_L2_cache();
- northbridgeinit();
- /* cpubug(); GX3*/
- chipsetinit(nb);
- setup_lx();
- /* do this here for now -- this chip really breaks our device model */
- setup_realmode_idt();
- do_vsmbios();
- graphics_init();
+ printk(BIOS_SPEW, ">> Entering northbridge.c: %s with path %d\n",
+ __func__, dev->path.type);
+
+ /* Set the operations if it is a special bus type */
+ if (dev->path.type == DEVICE_PATH_PCI_DOMAIN)
dev->ops = &pci_domain_ops;
- pci_set_method(dev);
- ram_resource(dev, 0, 0, ((sizeram() - VIDEO_MB) * 1024) - SMM_SIZE);
- } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
- printk_debug("DEVICE_PATH_APIC_CLUSTER\n");
- dev->ops = &cpu_bus_ops;
- }
- printk_debug("lx north: end enable_dev\n");
+ else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER)
+ dev->ops = &cpu_bus_ops;
}
struct chip_operations northbridge_amd_lx_ops = {
CHIP_NAME("AMD LX Northbridge")
- .enable_dev = enable_dev,
+ .enable_dev = enable_dev,
};
projects / coreboot.git / blobdiff