Since some people disapprove of white space cleanups mixed in regular commits

[coreboot.git] / src / northbridge / amd / gx2 / raminit.c

diff --git a/src/northbridge/amd/gx2/raminit.c b/src/northbridge/amd/gx2/raminit.c
index e0b5d0e75ec3390e969c1824a3774dfd84c566f1..3f99cab8ee639d0bf679522319a1566da58db7e3 100644 (file)
--- a/src/northbridge/amd/gx2/raminit.c
+++ b/src/northbridge/amd/gx2/raminit.c
@@ -4,11 +4,6 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
 {
 }
 
-static void sdram_set_spd_registers(const struct mem_controller *ctrl) 
-{
-       
-}
-
 /* Section 6.1.3, LX processor databooks, BIOS Initialization Sequence
  * Section 4.1.4, GX/CS5535 GeodeROM Porting guide */
 static void sdram_enable(int controllers, const struct mem_controller *ctrl)
@@ -16,19 +11,6 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
        int i;
        msr_t msr;
 
-       /* 1. Initialize GLMC registers base on SPD values,
-        * Hard coded as XpressROM for now */
-       print_debug("sdram_enable step 1\r\n");
-       msr = rdmsr(0x20000018);
-       msr.hi = 0x10076013;
-       msr.lo = 0x00003000;
-       wrmsr(0x20000018, msr);
-
-       msr = rdmsr(0x20000019);
-       msr.hi = 0x18000108;
-       msr.lo = 0x696332a3;
-       wrmsr(0x20000019, msr);
-
        /* 2. clock gating for PMode */
        msr = rdmsr(0x20002004);
        msr.lo &= ~0x04;
@@ -39,13 +21,13 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
        msr = rdmsr(0x2000001a);
        msr.lo = 0x0101;
        wrmsr(0x2000001a, msr);
-       print_debug("sdram_enable step 2\r\n");
+       //print_debug("sdram_enable step 2\n");
 
        /* 3. release CKE mask to enable CKE */
        msr = rdmsr(0x2000001d);
        msr.lo &= ~(0x03 << 8);
        wrmsr(0x2000201d, msr);
-       print_debug("sdram_enable step 3\r\n");
+       //print_debug("sdram_enable step 3\n");
 
        /* 4. set and clear REF_TST 16 times, more shouldn't hurt
         * why this is before EMRS and MRS ? */
@@ -56,7 +38,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
                msr.lo &= ~(0x01 << 3);
                wrmsr(0x20000018, msr);
        }
-       print_debug("sdram_enable step 4\r\n");
+       //print_debug("sdram_enable step 4\n");
 
        /* 5. set refresh interval */
        msr = rdmsr(0x20000018);
@@ -68,7 +50,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
        msr.lo &= ~(0x03 << 6);
        msr.lo |=  (0x00 << 6);
        wrmsr(0x20000018, msr);
-       print_debug("sdram_enable step 5\r\n");
+       //print_debug("sdram_enable step 5\n");
 
        /* 6. enable DLL, load Extended Mode Register by set and clear PROG_DRAM */
        msr = rdmsr(0x20000018);
@@ -76,17 +58,17 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
        wrmsr(0x20000018, msr);
        msr.lo &= ~((0x01 << 28) | 0x01);
        wrmsr(0x20000018, msr);
-       print_debug("sdram_enable step 6\r\n");
+       //print_debug("sdram_enable step 6\n");
 
        /* 7. Reset DLL, Bit 27 is undocumented in GX datasheet,
-        * it is documented in LX datasheet  */ 
+        * it is documented in LX datasheet  */
        /* load Mode Register by set and clear PROG_DRAM */
        msr = rdmsr(0x20000018);
        msr.lo |=  ((0x01 << 27) | 0x01);
        wrmsr(0x20000018, msr);
        msr.lo &= ~((0x01 << 27) | 0x01);
        wrmsr(0x20000018, msr);
-       print_debug("sdram_enable step 7\r\n");
+       //print_debug("sdram_enable step 7\n");
 
        /* 8. load Mode Register by set and clear PROG_DRAM */
        msr = rdmsr(0x20000018);
@@ -94,7 +76,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
        wrmsr(0x20000018, msr);
        msr.lo &= ~0x01;
        wrmsr(0x20000018, msr);
-       print_debug("sdram_enable step 8\r\n");
+       //print_debug("sdram_enable step 8\n");
 
        /* wait 200 SDCLKs */
        for (i = 0; i < 200; i++)
@@ -102,7 +84,15 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 
        /* load RDSYNC */
        msr = rdmsr(0x2000001f);
-       msr.hi = 0x000ff300;
+       msr.hi = 0x000ff310;
+       /* the above setting is supposed to be good for "slow" ram. We have found that for
+        * some dram, at some clock rates, e.g. hynix at 366/244, this will actually
+        * cause errors. The fix is to just set it to 0x310. Tested on 3 boards
+        * with 3 different type of dram -- Hynix, PSC, infineon.
+        * I am leaving this comment here so that at some future time nobody is tempted
+        * to mess with this setting -- RGM, 9/2006
+        */
+       msr.hi = 0x00000310;
        msr.lo = 0x00000000;
        wrmsr(0x2000001f, msr);
 
@@ -112,6 +102,17 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
        msr.lo = 0x8ea0ad6a;
        wrmsr(0x4c00000f, msr);
 
-       /* DRAM working now?? */
+       /* Fixes from Jordan Crouse of AMD. */
+
+       /* make sure there is nothing stale in the cache */
+       __asm__("wbinvd\n");
+
+       print_debug("RAM DLL lock\n");
+       /* The RAM dll needs a write to lock on so generate a few dummy writes */
+       volatile unsigned long *ptr;
+       for (i=0;i<5;i++) {
+               ptr = (void *)i;
+               *ptr = (unsigned long)i;
+       }
 
 }