#include "../../../southbridge/amd/cs5536/cs5536.h"
#define VIDEO_MB 8
-extern void graphics_init(void);
-
#define NORTHBRIDGE_FILE "northbridge.c"
-/* todo: add a resource record. We don't do this here because this may be called when
+/* todo: add a resource record. We don't do this here because this may be called when
* very little of the platform is actually working.
*/
int
printk(BIOS_DEBUG, "%s(%p [%08X], %04X)\n", __func__, dev, pciAddr, irq_map);
/* The IRQ steering values (in hex) are effectively dcba, where:
- * <a> represents the IRQ for INTA,
+ * <a> represents the IRQ for INTA,
* <b> represents the IRQ for INTB,
* <c> represents the IRQ for INTC, and
* <d> represents the IRQ for INTD.
/*
* setup_gx2_cache
*
- * Returns the amount of memory (in KB) available to the system. This is the
+ * Returns the amount of memory (in KB) available to the system. This is the
* total amount of memory less the amount of memory reserved for SMM use.
*
- */
+ */
static int
setup_gx2_cache(void)
{
}
/* we have to do this here. We have not found a nicer way to do it */
-void
+static void
setup_gx2(void)
{
membytes = size_kb * 1024;
/* NOTE! setup_gx2_cache returns the SIZE OF RAM - RAMADJUST!
- * so it is safe to use. You should NOT at this point call
- * sizeram() directly.
+ * so it is safe to use. You should NOT at this point call
+ * sizeram() directly.
*/
/* we need to set 0x10000028 and 0x40000029 */
/*
- * These two descriptors cover the range from 1 MB (0x100000) to
+ * These two descriptors cover the range from 1 MB (0x100000) to
* SYSTOP (a.k.a. TOM, or Top of Memory)
*/
static void enable_shadow(device_t dev)
{
-
+
}
-static void northbridge_init(device_t dev)
+static void northbridge_init(device_t dev)
{
unsigned long m;
struct northbridge_amd_gx2_config *nb = (struct northbridge_amd_gx2_config *)dev->chip_info;
printk(BIOS_DEBUG, "northbridge: %s()\n", __func__);
-
+
enable_shadow(dev);
irq_init_steering(dev, nb->irqmap);
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
}
+#if 0
static void tolm_test(void *gp, struct device *dev, struct resource *new)
{
struct resource **best_p = gp;
*best_p = best;
}
-#if 0
static u32 find_pci_tolm(struct bus *bus)
{
struct resource *min;
return tolm;
}
#endif
+
+// FIXME handle UMA correctly.
#define FRAMEBUFFERK 4096
static void pci_domain_set_resources(device_t dev)
continue;
ramreg += 1 << (((mem_config & (DIMM_SZ << i)) >> (i + 8)) + 2);
}
-
+
tomk = ramreg << 10;
/* Sort out the framebuffer size */
.enable_resources = enable_childrens_resources,
.init = 0,
.scan_bus = pci_domain_scan_bus,
-};
+};
static void cpu_bus_init(device_t dev)
{
static void enable_dev(struct device *dev)
{
printk(BIOS_DEBUG, "gx2 north: enable_dev\n");
- void northbridgeinit(void);
- void chipsetinit(struct northbridge_amd_gx2_config *nb);
void do_vsmbios(void);
+
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
struct northbridge_amd_gx2_config *nb = (struct northbridge_amd_gx2_config *)dev->chip_info;
- extern void cpubug(void);
u32 tomk;
printk(BIOS_DEBUG, "DEVICE_PATH_PCI_DOMAIN\n");
/* cpubug MUST be called before setup_gx2(), so we force the issue here */
northbridgeinit();
- cpubug();
- chipsetinit(nb);
+ cpubug();
+ gx2_chipsetinit(nb);
setup_gx2();
do_vsmbios();
graphics_init();
struct chip_operations northbridge_amd_gx2_ops = {
CHIP_NAME("AMD GX (previously GX2) Northbridge")
- .enable_dev = enable_dev,
+ .enable_dev = enable_dev,
};